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Test Conditions
WM8521HC: AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
WM8521H9: AVDD = 9V, DVDD = 3.3V, AGND / DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
SNR (Terminology Note 1,2,3)
A-weighted
@ fs = 96kHz
96 dB
SNR (Terminology Note 1,2,3)
N
on A weighted @ fs =
48kHz
93 dB
THD (Note 3)
1kHz, 0dBFs -81 dB
Dynamic Range (Note 2)
1kHz, THD+N @
-60dBFs
91 96 dB
DAC Channel Separation
1kHz, 0dBFs 93 dB
Power Supply Rejection Ratio
PSRR 1kHz 100mVpp 46 dB
Analogue Output Levels
Gain Mismatch
Channel-to-channel
±1 %FSR
Minimum Resistance Load
To midrail or a.c.
coupled
5 k
Maximum Capacitance Load
5.6 nF
Output d.c. Level
AVDD/2 V
Power On Reset (POR)
POR Threshold
DVDD 1.56 V
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured A
weighted over a 20Hz to 20kHz bandwidth.
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use
such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic
specification values.
3. CAP pin decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
4. Power down refers to operation after MCLK has been stopped. Digital reset occurs 1.5
s after MCLK is stopped.
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with
no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
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MASTER CLOCK TIMING
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
System Clock Timing Information
MCLK Master clock pulse width
high
t
MCLKH
11 ns
MCLK Master clock pulse width
low
t
MCLKL
11 ns
MCLK Master clock cycle time
t
MCLKY
28 ns
MCLK Duty cycle
40:60 60:40
Time from MCLK stopping to
digital reset
1.5 12
s
DIGITAL AUDIO INTERFACE
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Audio Data Input Timing Information
BCLK cycle time
t
BCY
50 ns
BCLK pulse width high
t
BCH
20 ns
BCLK pulse width low
t
BCL
20 ns
LRCLK set-up time to BCLK
rising edge
t
LRSU
10 ns
LRCLK hold time from
BCLK rising edge
t
LRH
10 ns
DIN set-up time to BCLK
rising edge
t
DS
10 ns
DIN hold time from BCLK
rising edge
t
DH
10 ns
CLK
R
CLK
CH CL
C
Y
IN
R
SU
S
R
H
H
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DEVICE DESCRIPTION
GENERAL INTRODUCTION
The WM8521 is a high performance DAC designed for digital consumer audio applications requiring a
2Vrms output. The range of features make it ideally suited for use in DVD players, Digital TV, Digital
Set Top Boxes, AV receivers and other consumer audio equipment.
The WM8521 is a complete 2-channel stereo audio digital-to-analogue converter, including digital
interpolation filter, multi-bit sigma delta with dither, switched capacitor multi-bit stereo DAC and output
smoothing filters combined with 2Vrms outputs. It is fully compatible and an ideal partner for a range
of industry standard microprocessors, controllers and DSPs. A novel multi bit sigma-delta DAC design
is used, utilising a 128x oversampling rate, to optimise signal to noise performance and offer
increased clock jitter tolerance.
Control of internal functionality of the device is provided by hardware control (pin programmed).
Operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between clock
rates being automatically controlled. Sample rates (fs) from 8kHz to 192kHz are allowed provided the
appropriate system clock is input.
The audio data interface supports 16-bit right justified or 16-, 20-, 24-, 32-bit I
2
S interface formats. A
16bit DSP interface is also supported, enhancing the interface options for the user.
The device is packaged in a small 14-pin SOIC.
DAC CIRCUIT DESCRIPTION
The WM8521 DAC is designed to allow playback of 24-bit PCM audio or similar data with high
resolution and low noise and distortion. Sample rates from 8kHz to 192kHz may be used provided
that the ratio of sample rate (LRCLK) to master clock (MCLK) is maintained at one of the required
rates.
The two DACs on the WM8521 are implemented using sigma-delta oversampled conversion
techniques. These require that the PCM samples are digitally filtered and interpolated to generate a
set of samples at a much higher rate than the input rate. This sample stream is then digitally
modulated to generate a digital pulse stream that is then converted to analogue signals in a switched
capacitor DAC. The advantage of this technique is that the DAC is linearised using noise shaping
techniques, allowing the 24-bit resolution to be met using non-critical analogue components. A further
advantage is that the high sample rate at the DAC output means that smoothing filters on the output
of the DAC need only have fairly crude characteristics in order to remove the characteristic steps, or
images on the output of the DAC. To ensure that generation of tones characteristic to sigma-delta
convertors is not a problem, dithering is used in the digital modulator along with a higher order
modulator. The multi-bit switched capacitor technique used in the DAC reduces sensitivity to clock
jitter, and dramatically reduces out of band noise compared to switched current or single bit
techniques used in other implementations.
The voltage on the CAP pin is used as the reference for the DACs. Therefore the amplitude of the
signals at the DAC outputs will scale with the amplitude of the voltage at the CAP pin. An external
reference could be used to drive into the CAP pin if desired, with a value typically of about midrail
ideal for optimum performance. However driven in normal operation, an internal divider will set a
valve of AVDD/2 on the cap pin.
Typically an external low pass filter circuit will be used to remove residual out of band noise
characteristic of delta sigma converters. However, the advanced multi-bit DAC used in WM8521
produces far less out of band noise than single bit traditional sigma delta DACs, and so in many
applications this filter may be removed, or replaced with a simple RC pole.

WM8521CH9GED/R

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Audio D/A Converter ICs Stereo DAC, 2Vrms
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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