REV. B
AD9883A
–4–
Test AD9883ABST–110 AD9883ABST–140
Parameter Temp Level Min Typ Max Min Typ Max Unit
RESOLUTION 8 8 Bits
DC ACCURACY
Differential Nonlinearity 25°CI ±0.5 +1.25/–1.0 ± 0.5 +1.5/–1.0 LSB
Full VI +1.5/–1.0 +1.81/–1.0 LSB
Integral Nonlinearity 25°CI ±0.5 ± 1.85 ± 0.5 ± 1.85 LSB
Full VI ± 3.2 ± 3.2 LSB
ANALOG INPUT
Input Voltage Range
Minimum Full VI 0.5 0.5 V p-p
Maximum Full VI 1.0 1.0 V p-p
Gain Tempco 25°CV 100 100 ppm/°C
Input Bias Current 25°CIV 1 1 µA
Full IV 2 2 µA
Input Offset Voltage Full VI 7 75 7 75 mV
Input Full-Scale Matching Full VI 1.5 8.0 1.5 10.0 % FS
Offset Adjustment Range Full VI 46 49 52 46 49 52 % FS
REFERENCE OUTPUT
Output Voltage Full VI 1.19 1.25 1.33 1.19 1.25 1.33 V
Temperature Coefficient Full V ± 100 ± 100 ppm/°C
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 110 140 MSPS
Minimum Conversion Rate Full IV 10 10 MSPS
Data to Clock Skew Full IV –0.5 +2.0 –0.5 +2.0 ns
t
BUFF
Full VI 4.7 4.7 µs
t
STAH
Full VI 4.0 4.0 µs
t
DHO
Full VI 0 0 µs
t
DAL
Full VI 4.7 4.7 µs
t
DAH
Full VI 4.0 4.0 µs
t
DSU
Full VI 250 250 µs
t
STASU
Full VI 4.7 4.7 µs
t
STOSU
Full VI 4.0 4.0 µs
HSYNC Input Frequency Full IV 15 110 15 110 kHz
Maximum PLL Clock Rate Full VI 110 140 MHz
Minimum PLL Clock Rate Full IV 12 12 MHz
PLL Jitter 25°CIV 400 700
1
400 700
1
ps p-p
Full IV 1100
1
1100
1
ps p-p
Sampling Phase Tempco Full IV 15 15 ps/°C
DIGITAL INPUTS
Input Voltage, High (V
IH
) Full VI 2.5 2.5 V
Input Voltage, Low (V
IL
) Full VI 0.8 0.8 V
Input Current, High (I
IH
) Full V –1.0 –1.0 µA
Input Current, Low (I
IL
) Full V 1.0 1.0 µA
Input Capacitance +25°CV 3 3 pF
DIGITAL OUTPUTS
Output Voltage, High (V
OH
) Full VI V
D
– 0.1 V
D
– 0.1 V
Output Voltage, Low (V
OL
) Full VI 0.1 0.1 V
Duty Cycle, DATACK Full IV 45 50 55 45 50 55 %
Output Coding Binary Binary
Analog Interface
(V
D
= 3.3 V, V
DD
= 3.3 V, ADC Clock = Maximum Conversion Rate, unless otherwise noted.)
