REV. B
AD9883A
–6–
ABSOLUTE MAXIMUM RATINGS*
V
D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
D
to 0.0 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
D
to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD9883AKST-140 0°C to 70°C LQFP ST-80
AD9883AKST-110 0°C to 70°C LQFP ST-80
AD9883AKSTZ-110* 0°C to 70°C LQFP ST-80
AD9883AKSTZ-140* 0°C to 70°C LQFP ST-80
AD9883ABST-110 –40°C to +85°C LQFP ST-80
AD9883ABST-140 –40°C to +85°C LQFP ST-80
AD9883ABST-RL110 –40°C to +85°C LQFP ST-80
AD9883ABST-RL140 –40°C to +85°C LQFP ST-80
AD9883A/PCB 25°CEvaluation Board
*Lead-free product
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9883A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–7–
AD9883A
PIN CONFIGURATION
GND
GREEN <7>
GREEN <6>
GREEN <5>
GREEN <4>
GREEN <3>
GREEN <2>
GREEN <1>
GREEN <0>
GND
V
DD
BLUE <7>
BLUE <6>
BLUE <5>
BLUE <4>
BLUE <3>
BLUE <2>
BLUE <1>
BLUE <0>
GND
GND
GND
GND
GND
GND
GND
V
D
V
D
V
D
V
D
V
D
V
D
REF BYPASS
SDA
SCL
A0
R
AIN
G
AIN
B
AIN
SOGIN
80 79 78 77 76 71 70 69 68 67 66 6575 74 73 72 64 63 62 61
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
12
17
18
20
19
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD9883A
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
GND
V
DD
V
DD
RED <0>
RED <1>
RED <2>
RED <3>
RED <4>
RED <5>
RED <6>
RED <7>
V
DD
GND
DATACK
HSOUT
SOGOUT
GND
V
D
GND
VSOUT
GND
V
DD
V
DD
GND
GND
PV
D
PV
D
GND
MIDSCV
CLAMP
V
D
GND
COAST
HSYNC
VSYNC
GND
FILT
PV
D
PV
D
GND
Table I. Complete Pinout List
Pin Type Mnemonic Function Value Pin No.
I
nputs R
AIN
Analog Input for Converter R 0.0 V to 1.0 V 54
G
AIN
Analog Input for Converter G 0.0 V to 1.0 V 48
B
AIN
Analog Input for Converter B 0.0 V to 1.0 V 43
HSYNC Horizontal SYNC Input 3.3 V CMOS 30
VSYNC Vertical SYNC Input 3.3 V CMOS 31
SOGIN Input for Sync-on-Green 0.0 V to 1.0 V 49
CLAMP Clamp Input (External CLAMP Signal) 3.3 V CMOS 38
COAST PLL COAST Signal Input 3.3 V CMOS 29
Outputs Red [7:0] Outputs of Converter Red, Bit 7 is the MSB 3.3 V CMOS 70–77
Green [7:0] Outputs of Converter Green, Bit 7 is the MSB 3.3 V CMOS 2–9
Blue [7:0] Outputs of Converter Blue, Bit 7 is the MSB 3.3 V CMOS 12–19
DATACK Data Output Clock 3.3 V CMOS 67
HSOUT HSYNC Output (Phase-Aligned with DATACK) 3.3 V CMOS 66
VSOUT VSYNC Output (Phase-Aligned with DATACK) 3.3 V CMOS 64
SOGOUT Sync-on-Green Slicer Output 3.3 V CMOS 65
References REF BYPASS Internal Reference Bypass 1.25 V 58
MIDSCV Internal Midscale Voltage Bypass 37
FILT Connection for External Filter Components for Internal PLL 33
Power Supply V
D
Analog Power Supply 3.3 V 39, 42,
45, 46, 51, 52,
59, 62
V
DD
Output Power Supply 3.3 V 11, 22, 23, 69,
78, 79
PV
D
PLL Power Supply 3.3 V 26, 27, 34, 35
GND Ground 0 V 1, 10, 20, 21,
24, 25, 28, 32,
36, 40, 41, 44,
47, 50, 53, 60,
61, 63, 68, 80
Control SDA Serial Port Data I/O 3.3 V CMOS 57
SCL Serial Port Data Clock (100 kHz Maximum) 3.3 V CMOS 56
A0 Serial Port Address Input 1 3.3 V CMOS 55
REV. B
AD9883A
–8–
PIN FUNCTION DESCRIPTIONS
Pin Name Function
OUTPUTS
HSOUT Horizontal Sync Output
A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be pro-
grammed via serial bus registers. By maintaining alignment with DATACK and Data, data timing with respect to
horizontal sync can always be determined.
VSOUT Vertical Sync Output
A reconstructed and phase-aligned version of the video Vsync. The polarity of this output can be controlled via a serial
bus bit. The placement and duration in all modes is set by the graphics transmitter.
SOGOUT Sync-On-Green Slicer Output
This pin outputs either the signal from the Sync-on-Green slicer comparator or an unprocessed but delayed version of the
Hsync input. See the Sync Processing Block Diagram (Figure 12) to view how this pin is connected. (Note: Besides
slicing off SOG, the output from this pin gets no other additional processing on the AD9883A. Vsync separation is performed
via the sync separator.)
SERIAL PORT (2-Wire)
SDA Serial Port Data I/O
SCL Serial Port Data Clock
A0 Serial Port Address Input 1
For a full description of the 2-wire serial register and how it works, refer to the 2-Wire Serial Control Port section.
DATA OUTPUTS
RED Data Output, Red Channel
GREEN Data Output, Green Channel
BLUE Data Output, Blue Channel
The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed. When the sampling time is
changed by adjusting the PHASE register, the output timing is shifted as well. The DATACK and HSOUT outputs are also
moved, so the timing relationship among the signals is maintained. For exact timing information, refer to Figures 7, 8, and 9.
DATA CLOCK OUTPUT
DATACK Data Output Clock
This is the main clock output signal used to strobe the output data and HSOUT into external logic. It is produced by the
internal clock generator and is synchronous with the internal pixel sampling clock. When the sampling time is changed
by adjusting the PHASE register, the output timing is shifted as well. The Data, DATACK, and HSOUT outputs are all
moved, so the timing relationship among the signals is maintained.
INPUTS
R
AIN
Analog Input for Red Channel
G
AIN
Analog Input for Green Channel
B
AIN
Analog Input for Blue Channel
High impedance inputs that accept the Red, Green, and Blue channel graphics signals, respectively. (The three channels
are identical, and can be used for any colors, but colors are assigned for convenient reference.) They accommodate input
signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation.
HSYNC Horizontal Sync Input
This input receives a logic signal that establishes the horizontal timing reference and provides the frequency reference
for pixel clock generation. The logic sense of this pin is controlled by serial register 0EH Bit 6 (Hsync Polarity). Only
the leading edge of Hsync is active; the trailing edge is ignored. When Hsync Polarity = 0, the falling edge of Hsync is used.
When Hsync Polarity = 1, the rising edge is active. The input includes a Schmitt trigger for noise immunity, with a nominal
input threshold of 1.5 V.
VSYNC Vertical Sync Input
This is the input for vertical sync.
SOGIN Sync-on-Green Input
This input is provided to assist with processing signals with embedded sync, typically on the Green channel. The pin is
connected to a high speed comparator with an internally generated threshold. The threshold level can be programmed in
10 mV steps to any voltage between 10 mV and 330 mV above the negative peak of the input signal. The default voltage
threshold is 150 mV. When connected to an ac-coupled graphics signal with embedded sync, it will produce a noninverting
digital output on SOGOUT. (This is usually a composite sync signal, containing both vertical and horizontal sync infor mation
that must be separated before passing the horizontal sync signal to Hsync.) When not used, this input should be left
unconnected. For more details on this function and how it should be configured, refer to the Sync-on-Green section.

AD9883AKSTZ-140

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Display Interface IC 140MHz Analog interface -SGA FPD
Lifecycle:
New from this manufacturer.
Delivery:
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