AD73311
–16–
REV. B
OPERATION
Resetting the AD73311
The pin RESET resets all the control registers. All registers
are reset to zero indicating that the default SCLK rate
(DMCLK/8) and sample rate (DMCLK/2048) are at a mini-
mum to ensure that slow speed DSP engines can communicate
effectively. As well as resetting the control registers using the
RESET pin, the device can be reset using the RESET bit (CRA:7)
in Control Register A. Both hardware and software resets re-
quire 4 DMCLK cycles. On reset, DATA/PGM (CRA:0) is set
to 0 (default condition) thus enabling Program Mode. The reset
conditions ensure that the device must be programmed to the
correct settings after power-up or reset. Following a reset, the
SDOFS will be asserted 280 DMCLK cycles after RESET
going high. The data that is output following RESET and dur-
ing Program Mode is random and contains no valid information
until either data or mixed mode is set.
Power Management
The individual functional blocks of the AD73311 can be en-
abled separately by programming the power control register
CRC. It allows certain sections to be powered down if not re-
quired, which adds to the device’s flexibility in that the user
need not incur the penalty of having to provide power for a
certain section if it is not necessary to their design. The power
control register provides individual control settings for the major
functional blocks and also a global override that allows all sec-
tions to be powered up by setting the bit. Using this method the
user could, for example, individually enable a certain section,
such as the reference (CRC:5), and disable all others. The glo-
bal power-up (CRC:0) can be used to enable all sections but if
power-down is required using the global control, the reference
will still be enabled, in this case, because its individual bit is set.
Refer to Table XIII for details of the settings of CRC.
Operating Modes
There are five operating modes available on the AD73311. Two
of these—Analog Loop-Back and Digital Loop-Back—are
reserved as diagnostic modes with the other three, Program,
Data and Mixed Program/Data, being available for general
purpose use. The device configuration— register settings—can
be changed only in Program and Mixed Program/Data Modes.
In all modes, transfers of information to or from the device
occur in 16-bit packets, therefore the DSP engine’s SPORT
will be programmed for 16-bit transfers.
Table X. Control Word Description
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C/D R/W DEVICE ADDRESS REGISTER ADDRESS REGISTER DATA
Control Frame Description
Bit 15 Control/Data When set high, it signifies a control word in Program or Mixed Program/Data Modes. When
set low, it signifies a data word in Mixed Program/Data Mode or an invalid control word in
Program Mode.
Bit 14 Read/Write When set low, it tells the device that the data field is to be written to the register selected by
the register field setting provided the address field is zero. When set high, it tells the device
that the selected register is to be written to the data field in the input serial register and that
the new control word is to be output from the device via the serial output.
Bits 13–11 Device Address This 3-bit field holds the address information. Only when this field is zero is a device se-
lected. If the address is not zero, it is decremented and the control word is passed out of
the device via the serial output.
Bits 10–8 Register Address This 3-bit field is used to select one of the five control registers on the AD73311.
Bits 7–0 Register Data This 8-bit field holds the data that is to be written to or read from the selected register
provided the address field is zero.
Table IX. Control Register Map
Address (Binary) Name Description Type Width Reset Setting (Hex)
000 CRA Control Register A R/W 8 0x00
001 CRB Control Register B R/W 8 0x00
010 CRC Control Register C R/W 8 0x00
011 CRD Control Register D R/W 8 0x00
100 CRE Control Register E R/W 8 0x00
101 to 111 Reserved
