AD73311ARZ-REEL Datasheet AD73311LARSZ-REEL7, AD73311LARSZ, AD73311LARUZ | P28-P30

AD73311

–27–

REV. B

Good decoupling is important when using high speed devices.

All analog and digital supplies should be decoupled to AGND

and DGND respectively, with 0.1 µF ceramic capacitors in

parallel with 10 µF tantalum capacitors. To achieve the best

from these decoupling capacitors, they should be placed as close

as possible to the device, ideally right up against it. In systems

where a common supply voltage is used to drive both the AVDD

and DVDD of the AD73311, it is recommended that the

system’s AVDD supply be used. This supply should have the

recommended analog supply decoupling between the AVDD

pins of the AD73311 and AGND and the recommended digital

supply decoupling capacitors between the DVDD pin and

DGND.

DSP Programming Considerations

This section discusses some aspects of how the serial port of the

DSP should be configured and the implications of whether Rx

and Tx interrupts should be enabled.

DSP SPORT Configuration

Following are the key settings of the DSP SPORT required for

the successful operation with the AD73311:

• Configure for external SCLK.

• Serial Word Length = 16 bits.

• Transmit and Receive Frame Syncs required with every word.

• Receive Frame Sync is an input to the DSP.

• Transmit Frame Sync is an:

Input—in Frame Sync Loop-Back Mode

Output—in Nonframe Sync Loop-Back Mode.

• Frame Syncs occur one SCLK cycle before the MSB of the

• serial word.

• Frame Syncs are active high.

DSP SPORT Interrupts

If SPORT interrupts are enabled, it is important to note that the

active signals on the frame sync pins do not necessarily corre-

spond with the positions in time of where SPORT interrupts are

generated.

On ADSP-21xx processors, it is necessary to enable SPORT

interrupts and use Interrupt Service Routines (ISRs) to handle

Tx/Rx activity, while on the TMS320CSx processors it is pos-

sible to poll the status of the Rx and Tx registers, which means

that Rx/Tx activity can be monitored using a single ISR that

would ideally be the Tx ISR as the Tx interrupt will typically

occur before the Rx ISR.

AD73311

–28–

REV. B

APPENDIX A

Programming a Single AD73311 for Data Mode Operation

This section describes a typical sequence in programming a

single codec to operate in normal DATA mode. It details the

control (program) words that are sent to the device to configure

its internal registers and shows the typical output data received

during both program and data modes. The device is connected

in Frame Sync Loop-Back Mode (see Figure 13), which forces

an input word from the DSP’s Tx Reg each time the codec

outputs a word via the SDO/SDOFS lines. In Step 1, the part

has just been reset and on the first output event the codec pre-

sents an invalid output word

. The DSP’s Tx Reg contains a

DSP TX REG

CONTROL WORD 1

1 0 000 001 00000011

ADC WORD 1 *

0000 0000 0000 0000

DON'T CARE

XXXX XXXX XXXX XXXX

DSP RX REG

STEP 1

DSP TX REG

DEVICE 1

CONTROL WORD 1

1 0 000 010 00000001

CONTROL WORD 1

1 0 000 001 00000011

ADC WORD 1 *

0000 0000 0000 0000

DSP RX REG

STEP 2

DSP TX REG

DEVICE 1

CONTROL WORD 1

1 0 000 010 00000001

ADC WORD 1 *

1011 1001 0000 0011

DON'T CARE

XXXX XXXX XXXX XXXX

DSP RX REG

STEP 3

DSP TX REG

DEVICE 1

CONTROL WORD 1

1 0 000 000 00000001

CONTROL WORD 1

1 0 000 010 00000001

ADC WORD 1 *

1011 1001 0000 0011

DSP RX REG

STEP 4

DSP TX REG DEVICE 1

CONTROL WORD 1

1 0 000 000 00000001

ADC WORD 1 *

1011 1010 0000 0001

DON'T CARE

XXXX XXXX XXXX XXXX

DSP RX REG

STEP 5

DSP TX REG

DEVICE 1

DAC WORD 1

0111 1111 1111 1111

CONTROL WORD 1

1 0 000 000 00000001

ADC WORD 1 *

1011 1010 0000 0001

DSP RX REG

STEP 6

DSP TX REG

DAC WORD 1

0111 1111 1111 1111

ADC WORD 1

1000 0000 0000 0000

DON'T CARE

XXXX XXXX XXXX XXXX

DSP RX REG

STEP 7

DSP TX REG

DEVICE 1

DAC WORD 1

0111 1111 1111 1111

DAC WORD 1

0111 1111 1111 1111

ADC WORD 1

1000 0000 0000 0000

DSP RX REG

STEP 8

*ADC SAMPLES DURING PROGRAM MODE ARE INVALID.

DEVICE 1

Figure 33. Programming a Single AD73311 for Normal

control word that programs CRB with the data word 0x03. In

Step 2, the control word from the DSP’s Tx Reg has been sent

to the codec’s SPORT and the output word has been received

by the DSP’s Rx Reg. In Steps 3 and 4, register CRC is pro-

grammed with 0x01, which powers up the analog section. In

Steps 5 and 6, the codec is put into programming mode by

setting the PGM/DATA bit of CRA. In Step 7, the output word

from the device is now a valid ADC word as the device has been

programmed into data mode. Note also that the codec now

expects DAC data to be sent to it and will interpret any data

from the DSP to be 16-bit DAC data.

NOTE

Data output by the codec in program mode is invalid and should not be inter-

preted as ADC data. The only exception to this is output caused by register

reads or CEE being enabled on control word writes.

AD73311

–29–

REV. B

APPENDIX B

Programming a Single AD73311 for Mixed Mode Operation

This section describes a typical sequence in programming a

single codec to operate in mixed mode. The device is connected

in Nonframe Sync Loop-Back Mode (see Figure 14), which

allows the DSP’s Tx Reg to determine how many words are sent

to the device. In Step 1, the part has just been reset and on the

first output event the codec presents an invalid output word

The DSP’s Tx Reg contains a control word that programs CRA

with the data word 0x03, which will put the device in mixed

mode. In Step 2, the control word from the DSP’s Tx Reg has

been sent to the codec’s SPORT and the output word has been

received by the DSP’s Rx Reg. The Tx Register raises the

SDIFS to send a control word that will program CRB of the

codec. In Step 3 the SCLK and sample rate are set by program-

ming CRB. In Step 4, the analog sections of the device are

powered up by programming CRC, while in Step 5, the encoder

gain is set to 0 dB via CRD. In Step 6, the DAC register is

updated by the contents of the serial register. Alternately, a

in Step 6

. Steps 7 and 8 show another ADC read, DAC write

cycle.

NOTES

Data output by the codec in program mode is invalid and should not be inter-

preted as ADC data. The only exception to this is output caused by register

reads or CEE being enabled on control word writes.

In mixed mode, it may be necessary to terminate a control word write to a

device with a control word read to that device in order to ensure that the next

ADC sample is correct. Alternatively the ADC word can either be discarded or,

if this is not possible, it can be rebuilt by incrementing the “address field”

within the 16-bit word.

DSP TX REG

CONTROL WORD 1

1 0 000 000 00000011

ADC WORD 1 *

0000 0000 0000 0000

DON'T CARE

XXXX XXXX XXXX XXXX

STEP 1

DSP TX REG

DEVICE 1

CONTROL WORD 1

1 0 000 001 00001111

CONTROL WORD 1

1 0 000 000 00000011

ADC WORD 1 *

0000 0000 0000 0000

DSP RX REG

STEP 2

DSP TX REG

DEVICE 1

CONTROL WORD 1

1 0 000 010 00000001

CONTROL WORD 1

1 0 000 001 00001111

DON'T CARE

XXXX XXXX XXXX XXXX

DSP RX REG

STEP 3

DSP TX REG

DEVICE 1

CONTROL WORD 1

1 0 000 000 00000001

CONTROL WORD 1

1 0 000 010 00000001

DON'T CARE

XXXX XXXX XXXX XXXX

DSP RX REG

STEP 4

DSP TX REG

DEVICE 1

DAC WORD 1

0100 0000 0000 0000

CONTROL WORD 1

1 0 000 011 00100000

DON'T CARE

XXXX XXXX XXXX XXXX

DSP RX REG

STEP 5

DSP TX REG

DEVICE 1

DAC WORD 1

0011 1111 1111 1111

DAC WORD 1

0100 0000 0000 0000

DON'T CARE

XXXX XXXX XXXX XXXX

DSP RX REG

STEP 6

DSP TX REG

DAC WORD 1

0011 1111 1111 1111

ADC WORD 1

0100 0000 0000 0000

DON'T CARE

XXXX XXXX XXXX XXXX

DSP RX REG

STEP 7

DSP TX REG DEVICE 1

DAC WORD 1

0100 0000 0000 0000

DAC WORD 1

0011 1111 1111 1111

ADC WORD 1

1000 0000 0000 0000

DSP RX REG

STEP 8

*ADC SAMPLES DURING PROGRAM MODE ARE INVALID.

DEVICE 1

DSP RX REG

DEVICE 1

Figure 34. Programming a Single AD73311 for Mixed Mode

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P37

AD73311ARZ-REEL

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Manufacturer:

Analog Devices Inc.

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Analog Front End - AFE SGL-Ch 3-5V Front-End Processor

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