AD73311
–30–
REV. B
APPENDIX C
Configuring a Cascade of Two AD73311s to Operate in
Data Mode
This section describes a typical sequence of control words that
would be sent to a cascade of two AD73311s to set them up for
operation. It is not intended to be a definitive initialization
sequence, but will show users the typical input/output events
that occur in the programming and operation phases
1
. This
description panel refers to Figure 35.
In Step 1, we have the first output sample event following device
reset. The SDOFS signal is raised on both devices simulta-
neously, which prepares the DSP Rx register to accept the ADC
word from Device 2, while SDOFS from Device 1 becomes an
SDIFS to Device 2. As the SDOFS of Device 2 is coupled to
the DSP’s TFS and RFS, and to the SDIFS of Device 1, this
event also forces a new control word to be output from the DSP
Tx register to Device 1.
In Step 2, we observe the status of the devices following the
transmission of the first control word. The DSP has received the
ADC word from Device 2, while Device 2 has received the
ADC word from Device 1 and Device 1 has received the Con-
trol word destined for Device 2. At this stage, the SDOFS of
both devices are again raised because Device 2 has received
Device 1’s ADC word, and as it is not a valid control word
addressed to Device 2, it is passed on to the DSP. Likewise,
Device 1 has received a control word destined for Device 2—
address field is not zero—and it decrements the address field of
the control word and passes it on.
Step 3 shows completion of the first series of control word
writes. The DSP has now received both invalid ADC words and
each device has received a control word that addresses control
register B and sets the internal MCLK divider ratio to 1, SCLK
rate to DMCLK/8. Note that both devices are updated simulta-
neously as both receive the addressed control word at the same
time. This is an important factor in cascaded operation as any
latency between updating the SCLK or DMCLK of devices can
result in corrupted operation. This will not happen in the case
of a FSLB configuration as shown here, but must be taken into
account in a non-FSLB configuration. One other important
observation of this sequence is that the data words are received
and transmitted in reverse order, i.e., the ADC words are
received by the DSP, Device 2 first, then Device 1, and similarly
the transmit words from the DSP are sent Device 2 first, then
Device 1. This ensures that all devices are updated at the same
time.
In Step 4, the next ADC sample event that happens raises the
SDOFS lines of each of the devices. The DSP Tx register con-
tains the first of the two control words to be written to the cas-
cade—the word for Device 2.
In Step 5, following transmission of the first of the two control
words, the DSP Rx register contains Device 2’s ADC word,
Device 2’s serial register contains the Device 1 ADC word,
Device 1’s serial register contains the control word addressed to
Device 2 and the DSP Tx register contains the next control
word—that addressed to Device 1. Again, both devices raise
their SDOFS lines as both have received control words not
addressed to them.
Step 6 shows the completion of the second set of control word
writes. In this case, both devices have received a control word
addressed to control register A, which sets the device count field
equal to two devices in cascade and sets the PGM/DATA bit to
one to put the device in data mode.
In Step 7, the programming phase is complete and we now
begin actual device data read and write. The words loaded into
the serial registers of the two devices at the ADC sampling event
now contain valid ADC data and the words written to the de-
vices from the DSP’s Tx register will now be interpreted as
DAC words. Note, therefore, that the DSP Tx register contains
the DAC word for Device 2.
In Step 8, the first DAC word has been transmitted into the
cascade and the ADC word from Device 2 has been read from
the cascade. The DSP Tx register now contains the DAC word
for Device 1. As the words being sent to the cascade are now
being interpreted as 16-bit DAC words, the addressing scheme
now changes from one where the address was embedded in the
transmitted word to one where the serial port now counts the
SDIFS pulses. When the number of SDIFS pulses received
equals the value in the device count field of control register A—
the length of the cascade—each device updates its DAC register
with the present word in its serial register. In Step 8 each device
has received only one SDIFS pulse; Device 2 received one
SDIFS from the SDOFS of Device 1 when it sent its ADC word
and Device 1 received one SDIFS pulse when it received the
DAC word for Device 2 from the DSP’s Tx register. Therefore,
each device raises its SDOFS line to pass on the current word in
its serial register, and each device now receives another SDIFS
pulse.
Step 9 shows the completion of an ADC read and DAC write
cycle. Following Step 8, each device has received two SDIFS
pulses that equal the setting of the device count field in Control
Register A. The DAC register in each device is now updated
with the contents of the word that accompanied the SDIFS
pulse which satisfied the device count requirement. The internal
frame sync counter is now reset to zero and will begin counting
for the next DAC update cycle.
NOTE
1
This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are enabled.
It is important to ensure that there is no latency (separation) between control
words in a cascade configuration. This is especially the case when programming
Control Register B as it contains settings for SCLK and DMCLK rates.
