AD73311
–9–
REV. B
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
AVDD, DVDD to GND . . . . . . . . . . . . . . . . . 0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . .0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . 0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . 40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . +150°C
SOIC, θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . 75° C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
SSOP, θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . 90°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature Package
Model Range Option
1
AD73311AR 40°C to +85°C R-20
AD73311ARS 40°C to +85°C RS-20
EVAL-AD73311EB Evaluation Board
2
+EZ-KIT Lite Upgrade
3
EVAL-AD73311EZ Evaluation Board
2
+EZ-KIT Lite
4
NOTES
1
R = 0.3' Small Outline IC (SOIC), RS = Shrink Small Outline Package (SSOP).
2
The AD73311 evaluation board features a selectable number of codecs in
cascade (from 1 to 4). It can be interfaced to an ADSP-2181 EZ-KIT Lite or
to a Texas Instruments EVM kit.
3
The upgrade consists of a replacement PROM and connector. This option is
intended for existing owners of EZ-KIT Lite.
4
The EZ-KIT Lite has been modified to allow it to interface with the AD73311
evaluation board. This option is intended for users who do not already have an
EZ-KIT Lite.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD73311 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
VOUTP
SDOFS
SDIFS
SDI
SE
VOUTN
AVDD1
AGND1
AD73311
SCLK
MCLK
SDOVINP
VINN
REFOUT
REFCAP
AVDD2
AGND2
DGND
DVDD
RESET
WARNING!
ESD SENSITIVE DEVICE
AD73311
–10–
REV. B
PIN FUNCTION DESCRIPTIONS
Pin
Number Mnemonic Function
1 VOUTP Analog Output from the Positive Terminal of the Output Channel.
2 VOUTN Analog Output from the Negative Terminal of the Output Channel.
3 AVDD1 Analog Power Supply Connection for the Output Driver.
4 AGND1 Analog Ground Connection for the Output Driver.
5 VINP Analog Input to the Positive Terminal of the Input Channel.
6 VINN Analog Input to the Negative Terminal of the Input Channel.
7 REFOUT Buffered Reference Output, which has a nominal value of 1.2 V or 2.4 V, the value being dependent
on the status of Bit 5VEN (CRC:7).
8 REFCAP A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should
be fixed to this pin.
9 AVDD2 Analog Power Supply Connection.
10 AGND2 Analog Ground/Substrate Connection.
11 DGND Digital Ground/Substrate Connection.
12 DVDD Digital Power Supply Connection.
13 RESET Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing
the digital circuitry.
14 SCLK Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock
data or control information to and from the serial port (SPORT). The frequency of SCLK is equal to
the frequency of the master clock (MCLK) divided by an integer numberthis integer number being
the product of the external master clock rate divider and the serial clock rate divider.
15 MCLK Master Clock Input. MCLK is driven from an external clock signal.
16 SDO Serial Data Output of the Codec. Both data and control information may be output on this pin and is
clocked on the positive edge of SCLK. SDO is in three-state when no information is being transmitted
and when SE is low.
17 SDOFS Framing Signal Output for SDO Serial Transfers. The frame sync is one-bit wide and it is active one
SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positive
edge of SCLK. SDOFS is in three-state when SE is low.
18 SDIFS Framing Signal Input for SDI Serial Transfers. The frame sync is one-bit wide and it is valid one
SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of
SCLK and is ignored when SE is low.
19 SDI Serial Data Input of the Codec. Both data and control information may be input on this pin and are
clocked on the negative edge of SCLK. SDI is ignored when SE is low.
20 SE SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the
output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled
internally in order to decrease power dissipation. When SE is brought high, the control and data regis-
ters of the SPORT are at their original values (before SE was brought low), however the timing
counters and other internal registers are at their reset values.
AD73311
–11–
REV. B
TERMINOLOGY
Absolute Gain
Absolute gain is a measure of converter gain for a known signal.
Absolute gain is measured (differentially) with a 1 kHz sine
wave at 0 dBm0 for the DAC and with a 1 kHz sine wave at
0 dBm0 for the ADC. The absolute gain specification is used for
gain tracking error specification.
Crosstalk
Crosstalk is due to coupling of signals from a given channel
to an adjacent channel. It is defined as the ratio of the amplitude
of the coupled signal to the amplitude of the input signal.
Crosstalk is expressed in dB.
Gain Tracking Error
Gain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz
for the DAC and 0 dBm0 (equal to absolute gain) at 1 kHz for
the ADC. Gain tracking error at 0 dBm0 (ADC) and 0 dBm0
(DAC) is 0 dB by definition.
Group Delay
Group Delay is defined as the derivative of radian phase with
respect to radian frequency, dø(f)/df. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay from a constant indicates the
degree of nonlinear phase response of the system.
Idle Channel Noise
Idle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (mea-
sured in the frequency range 300 Hz3400 Hz).
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For final testing, the second
order terms include (fa + fb) and (fa fb), while the third order
terms include (2fa + fb), (2fa fb), (fa + 2fb) and (fa 2fb).
Power Supply Rejection
Power supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).
Sample Rate
The sample rate is the rate at which the ADC updates its output
register and the DAC updates its output from its input register.
It is fixed relative to the DMCLK (= DMCLK/256) and there-
fore may only be changed by changing the DMCLK.
SNR+THD
Signal-to-noise ratio plus harmonic distortion is defined to be
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in the frequency range
300 Hz3400 Hz, including harmonics but excluding dc.
ABBREVIATIONS
ADC Analog-to-Digital Converter.
ALB Analog Loop-Back.
BW Bandwidth.
CRx A Control Register where x is a placeholder for an
alphabetic character (AE). There are five read/
write control registers on the AD73311desig-
nated CRA through CRE.
CRx:n A bit position, where n is a placeholder for a nu-
meric character (07), within a control register;
where x is a placeholder for an alphabetic charac-
ter (AE). Position 7 represents the MSB and
Position 0 represents the LSB.
DAC Digital-to-Analog Converter.
DLB Digital Loop-Back.
DMCLK Device (Internal) Master Clock. This is the inter-
nal master clock resulting from the external master
clock (MCLK) being divided by the on-chip mas-
ter clock divider.
FSLB Frame Sync Loop Backwhere the SDOFS of
the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of
first device in the cascade. Data input and out-
put occur simultaneously. In the case of Non-
FSLB, SDOFS and SDO are connected to the
Rx Port of the DSP while SDIFS and SDI are
connected to the Tx Port.
PGA Programmable Gain Amplifier.
SC Switched Capacitor.
SNR Signal-to-Noise Ratio.
SPORT Serial Port.
THD Total Harmonic Distortion.
VBW Voice Bandwidth.

AD73311LARSZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE SGL-Ch 3-5V Front-End Processor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union