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AD73311LARSZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
AD73311A
Parameter Min Typ Max Unit Test Conditions/Comments
DAC SPECIFICATIONS (Continued)
Power Supply Rejection –55 dB Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Group Delay
4, 5
25 µs 64 kHz Input Sample Rate, Interpolator
Bypassed (CRE:5 = 1)
Output DC Offset
2, 7
–30 +20 +70 mV PGA = 6 dB
Minimum Load Resistance, R
L
2, 8
Single-Ended 150 Ω
Differential 150 Ω
Maximum Load Capacitance, C
L
2, 8
Single-Ended 500 pF
Differential 100 pF
FREQUENCY RESPONSE
(ADC AND DAC)
9
Typical Output
0 Hz 0 dB
2000 Hz –0.1 dB
4000 Hz –0.25 dB
8000 Hz –0.6 dB
12000 Hz –1.4 dB
16000 Hz –2.8 dB
20000 Hz –4.5 dB Channel Frequency Response Is
24000 Hz –7.0 dB Programmable by Means of External
28000 Hz –9.5 dB Digital Filtering
> 32000 Hz < –12.5 dB
LOGIC INPUTS
V
INH
, Input High Voltage V
DD
– 0.8 V
DD
V
V
INL
, Input Low Voltage 0 0.8 V
I
IH
, Input Current 10 µA
C
IN
, Input Capacitance 10 pF
LOGIC OUTPUT
V
OH
, Output High Voltage V
DD
– 0.4 V
DD
V |IOUT| ≤ 100 µA
V
OL
, Output Low Voltage 0 0.4 V |IOUT| ≤ 100 µA
Three-State Leakage Current –10 +10 µA
POWER SUPPLIES
AVDD1, AVDD2 2.7 3.3 V
DVDD 2.7 3.3 V
I
DD
10
See Table I
NOTES
1
Operating temperature range is as follows: –40°C to +85°C. Therefore, T
MIN
= –40°C and T
MAX
= +85°C.
2
Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).
3
At input to sigma-delta modulator of ADC.
4
Guaranteed by design.
5
Overall group delay will be affected by the sample rate and the external digital filtering.
6
The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 10
11
)/DMCLK.
7
Between VOUTP and VOUTN.
8
At VOUT output.
9
Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
10
Test Conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
Table I. Current Summary (AVDD = DVDD = +3.3 V)
Analog Internal Digital External Interface Total Current MCLK
Conditions Current Current Current (Max) SE ON Comments
ADC On Only 7 3 0.5 11.5 1 YES REFOUT Disabled
ADC and DAC On 10 5 0.5 17.5 1 YES REFOUT Disabled
REFCAP On Only 0.75 0 0 1.2 0 NO REFOUT Disabled
REFCAP and
REFOUT On Only 3.0 0 0 4.5 0 NO
All Sections Off 0 0.85 0 1.2 0 YES MCLK Active Levels Equal to
0 V and DVDD
All Sections Off 0.00 0.007 0 0.04 0 NO Digital Inputs Static and Equal
to 0 V or DVDD
The above values are in mA and are typical values unless otherwise noted.
AD73311
–3–
REV. B
(AVDD = +5 V ⴞ 10%; DVDD = +5 V ⴞ 10%; DGND = AGND = 0 V, f
MCLK
= 16.384 MHz,
F
S
= 64 kHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted)
AD73311A
Parameter Min Typ Max Unit Test Conditions/Comments
REFERENCE
REFCAP
Absolute Voltage, V
REFCAP
1.2 V 5VEN = 0
2.4 V 5VEN = 1
REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from
REFOUT REFCAP to AGND2
Typical Output Impedance 68 Ω
Absolute Voltage, V
REFOUT
1.2 V 5VEN = 0, Unloaded
2.4 V 5VEN = 1, Unloaded
Minimum Load Resistance 2 kΩ 5VEN = 1
Maximum Load Capacitance 100 pF
ADC SPECIFICATIONS
Maximum Input Range at VIN
2, 3
3.156 V p-p 5VEN = 1, Measured Differentially
3.17 dBm
Nominal Reference Level at VIN 2.1908 V p-p 5VEN = 1, Measured Differentially
(0 dBm0) 0 dBm
Absolute Gain
PGA = 0 dB 0.1 dB 1.0 kHz, 0 dBm0
PGA = 38 dB –0.5 dB 1.0 kHz, 0 dBm0
Gain Tracking Error ± 0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion) Refer to Figure 5
PGA = 0 dB 76 dB 300 Hz to 3.4 kHz Frequency Range
59 dB 0 Hz to 32 kHz Frequency Range
PGA = 38 dB 71 dB 300 Hz to 3.4 kHz Frequency Range
57 dB 0 Hz to 32 kHz Frequency Range
Total Harmonic Distortion
PGA = 0 dB –76 dB
PGA = 38 dB –69 dB
Intermodulation Distortion –69 dB PGA = 0 dB
Idle Channel Noise –67 dBm0 PGA = 0 dB
Crosstalk –80 dB ADC Input Signal Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
DC Offset +20 mV PGA = 0 dB
Power Supply Rejection –55 dB Input Signal Level at AVDD and DVDD
Pins 1.0 kHz, 100 mV p-p Sine Wave
Group Delay
4, 5
25 µs 64 kHz Output Sample Rate
Input Resistance at VIN
2, 4
25 kΩ
6
DMCLK = 16.384 MHz
DAC SPECIFICATIONS
Maximum Voltage Output Swing
2
Single Ended 3.156 V p-p 5VEN = 1, PGA = 6 dB
3.17 dBm
Differential 6.312 V p-p 5VEN = 1, PGA = 6 dB
9.19 dBm
Nominal Voltage Output Swing (0 dBm0)
Single-Ended 2.1908 V p-p 5VEN = 1, PGA = 6 dB
0 dBm
Differential 4.3918 V p-p 5VEN = 1, PGA = 6 dB
6.02 dBm
Output Bias Voltage V
REFOUT
V typ 5VEN = 1, REFOUT Unloaded
Absolute Gain ± 0.4 dB 1.0 kHz, 0 dBm0
Gain Tracking Error ± 0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion) Refer to Figure 5
PGA = 0 dB 66 dB 300 Hz to 3.4 kHz Frequency Range
64 dB 0 Hz to 32 kHz Frequency Range
PGA = 6 dB 66 dB 300 Hz to 3.4 kHz Frequency Range
64 dB 0 Hz to 32 kHz Frequency Range
Total Harmonic Distortion
PGA = 0 dB –62.5 dB
PGA = 6 dB –62.5 dB
Intermodulation Distortion –60 dB PGA = 0
Idle Channel Noise –75 dBm0 PGA = 0
Crosstalk –80 dB ADC Input Signal Level: AGND; DAC
Output Signal Level: 1.0 kHz, 0 dBm0
AD73311–SPECIFICATIONS
1
–4–
REV. B
–5–
REV. B
AD73311
AD73311A
Parameter Min Typ Max Unit Test Conditions/Comments
DAC SPECIFICATIONS (Continued)
Power Supply Rejection –55 dB Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Group Delay
4, 5
25 µs 64 kHz Input Sample Rate, Interpolator
Bypassed (CRE:5 = 1)
Output DC Offset
2, 7
+30 mV PGA = 6 dB
Minimum Load Resistance, R
L
2, 8
Single-Ended 150 Ω
Differential 150 Ω
Maximum Load Capacitance, C
L
2, 8
Single-Ended 500 pF
Differential 100 pF
FREQUENCY RESPONSE
(ADC AND DAC)
9
Typical Output
0 Hz 0 dB
2000 Hz –0.1 dB
4000 Hz –0.25 dB
8000 Hz –0.6 dB
12000 Hz –1.4 dB
16000 Hz –2.8 dB
20000 Hz –4.5 dB Channel Frequency Response Is
24000 Hz –7.0 dB Programmable by Means of External
28000 Hz –9.5 dB Digital Filtering
> 32000 Hz < –12.5 dB
LOGIC INPUTS
V
INH
, Input High Voltage V
DD
– 0.8 V
DD
V
V
INL
, Input Low Voltage 0 0.8 V
I
IH
, Input Current –0.5 µA
C
IN
, Input Capacitance 10 pF
LOGIC OUTPUT
V
OH
, Output High Voltage V
DD
– 0.4 V
DD
V|I
OUT
| < 100 µA
V
OL
, Output Low Voltage 0 0.4 V |I
OUT
| < 100 µA
Three-State Leakage Current –0.3 µA
POWER SUPPLIES
AVDD1, AVDD2 4.5 5.5 V
DVDD 4.5 5.5 V
I
DD
10
See Table II
N
OTES
1
Operating temperature range is as follows: –40°C to +85°C. Therefore, T
MIN
= –40°C and T
MAX
= +85°C.
2
Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise stated).
3
At input to sigma-delta modulator of ADC.
4
Guaranteed by design.
5
Overall group delay will be affected by the sample rate and the external digital filtering.
6
The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 10
11
)/DMCLK.
7
Between VOUTP and VOUTN.
8
At VOUT output.
9
Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
10
Test conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

AD73311LARSZ

Mfr. #:
Buy AD73311LARSZ
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE SGL-Ch 3-5V Front-End Processor
Lifecycle:
New from this manufacturer.
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