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MC14511BDR2G
P1-P3
P4-P6
P7-P9
P10-P10
MC1451
1B
http://onsemi.com
4
SWITCHING CHARACTERISTICS
(Note 7)
(C
L
= 50 pF, T
A
= 25
°
C)
Characteristic
Symbol
V
DD
Vdc
Min
Ty
p
Max
Unit
Output Rise T
ime
t
TLH
= (0.40 ns/pF) C
L
+ 20 ns
t
TLH
= (0.25 ns/pF) C
L
+ 17.5 ns
t
TLH
= (0.20 ns/pF) C
L
+ 15 ns
t
TLH
5.0
10
15
−
−
−
40
30
25
80
60
50
ns
Output Fall T
ime
t
THL
= (1.5 ns/pF) C
L
+ 50 ns
t
THL
= (0.75 ns/pF) C
L
+ 37.5 ns
t
THL
= (0.55 ns/pF) C
L
+ 37.5 ns
t
THL
5.0
10
15
−
−
−
125
75
65
250
150
130
ns
Data Propagation Delay T
ime
t
PLH
= (0.40 ns/pF) C
L
+ 620 ns
t
PLH
= (0.25 ns/pF) C
L
+ 237.5 ns
t
PLH
= (0.20 ns/pF) C
L
+ 165 ns
t
PHL
= (1.3 ns/pF) C
L
+ 655 ns
t
PHL
= (0.60 ns/pF) C
L
+ 260 ns
t
PHL
= (0.35 ns/pF) C
L
+ 182.5 ns
t
PLH
5.0
10
15
−
−
−
640
250
175
1280
500
350
ns
t
PHL
5.0
10
15
−
−
−
720
290
200
1440
580
400
Blank
Propagation Delay T
ime
t
PLH
= (0.30 ns/pF) C
L
+ 585 ns
t
PLH
= (0.25 ns/pF) C
L
+ 187.5 ns
t
PLH
= (0.15 ns/pF) C
L
+ 142.5 ns
t
PHL
= (0.85 ns/pF) C
L
+ 442.5 ns
t
PHL
= (0.45 ns/pF) C
L
+ 177.5 ns
t
PHL
= (0.35 ns/pF) C
L
+ 142.5 ns
t
PLH
5.0
10
15
−
−
−
600
200
150
750
300
220
ns
t
PHL
5.0
10
15
−
−
−
485
200
160
970
400
320
Lamp T
est
Propagation Delay T
ime
t
PLH
= (0.45 ns/pF) C
L
+ 290.5 ns
t
PLH
= (0.25 ns/pF) C
L
+ 1
12.5 ns
t
PLH
= (0.20 ns/pF) C
L
+ 80 ns
t
PHL
= (1.3 ns/pF) C
L
+ 248 ns
t
PHL
= (0.45 ns/pF) C
L
+ 102.5 ns
t
PHL
= (0.35 ns/pF) C
L
+ 72.5 ns
t
PLH
5.0
10
15
−
−
−
313
125
90
625
250
180
ns
t
PHL
5.0
10
15
−
−
−
313
125
90
625
250
180
Setup T
ime
t
su
5.0
10
15
100
40
30
−
−
−
−
−
−
ns
Hold T
ime
t
h
5.0
10
15
60
40
30
−
−
−
−
−
−
ns
Latch Enable Pulse Width
t
WL
5.0
10
15
520
220
130
260
11
0
65
−
−
−
ns
7.
The formulas given are for the typical characteristics only
.
MC1451
1B
http://onsemi.com
5
Figure 1. Dynamic Power Dissipation Signal W
aveforms
Input LE low
, and Inputs D, BI
and L
T
high.
f in respect to a system clock.
All outputs connected to respective C
L
loads.
20 ns
20 ns
V
DD
V
SS
V
OH
V
OL
90%
50%
10%
50%
A, B, AND C
ANY OUTPUT
50% DUTY CYCLE
1
2f
Figure 2. Dynamic Signal W
aveforms
20 ns
20 ns
V
DD
90%
INPUT C
(a) Inputs D and LE low
, and
Inputs A, B, BI
and L
T
high.
V
SS
V
OH
V
OL
50%
10%
OUTPUT g
t
PLH
t
PHL
90%
10%
50%
t
TLH
t
THL
(b) Input D low
,
Inputs A, B, BI
and L
T
high.
20 ns
10%
90%
50%
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
t
h
t
su
50%
INPUT C
OUTPUT g
LE
(c) Data DCBA strobed into latches.
20 ns
20 ns
V
DD
V
SS
LE
90%
50%
10%
t
WL
MC1451
1B
http://onsemi.com
6
CONNECTIONS TO V
ARIOUS
DISPLA
Y READOUTS
COMMON
CA
THODE LED
≈
1.7 V
V
DD
V
SS
V
DD
COMMON
ANODE LED
V
SS
≈
1.7 V
LIGHT EMITTING DIODE (LED) READOUT
INCANDESCENT READOUT
FLUORESCENT READOUT
GAS DISCHARGE READOUT
LIQUID CR
YST
AL (LCD) READOUT
V
DD
V
DD
**
V
SS
V
DD
V
SS
FILAMENT
SUPPL
Y
DIRECT
(LOW BRIGHTNESS)
V
SS
OR APPROPRIA
TE
VOL
T
AGE BELOW V
SS
.
(CAUTION:
Maximum working voltage = 18.0 V
)
V
DD
APPROPRIA
TE
VOL
T
AGE
V
SS
V
SS
V
DD
EXCIT
A
TION
(SQUARE WA
VE,
V
SS
TO V
DD
)
1/4 OF MC14070B
**
A filament pre−warm resistor is recommended to reduce filament
thermal shock and increase the ef
fective cold resistance of
the
filament.
Direct DC drive of LCD’s not recommended for life of
LCD readouts.
P1-P3
P4-P6
P7-P9
P10-P10
MC14511BDR2G
Mfr. #:
Buy MC14511BDR2G
Manufacturer:
ON Semiconductor
Description:
Encoders, Decoders, Multiplexers & Demultiplexers LOG CMOS DSPLY DCODE DRVR
Lifecycle:
New from this manufacturer.
Delivery:
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