LT8584
22
8584fb
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applicaTions inForMaTion
Diode leakage current under high reverse bias bleeds the
output battery/capacitor stack of charge. Choose a diode
that has minimal reverse bias leakage current. Diode
junction capacitance is reflected back to the primary, and
energy is lost during negative NPN collection conduction.
Choose a diode with minimal junction capacitance. Table 4
recommends several output diodes for various output
voltages that have adequate reverse recovery times.
Flyback Output Capacitor
Every balancer flyback output must have a ceramic capaci
-
tor on its output. The output capacitor serves as a local,
low
impedance return path. It also aids during a connection
failure, adding charge storage to allow the OVP circuit to
detect an open. The capacitor should be sized to allow
roughly 10 switch cycles when charging the output from
ground to the nominal output voltage, V
OUTPUT,NOM
. Use
the following equation to size the output capacitor:
C
FBO
400 L
PRIMARY
V
2
OUTPUT,NOM
The voltage surge rating must exceed 50•N. The volt-
age surge rating is usually specified as a multiple of the
maxi
mum operating voltage. For capacitor maximum
operating voltages less than 100V, the surge rating is
2.5x. For operating voltage between 100V and 630V, the
surge rating is typically 1.5x; and for voltages higher than
1000V, the surge rating is 1.2x.
Bypass Capacitors
The LT8584 should be bypassed using 3 capacitors, C
VIN
,
C
VCELL
, and C
TRAN
(see Block Diagram), using a high-grade
(X5R or better) ceramic capacitors. C
VIN
should be placed
close to the V
IN
pin and should be sized betweenF and
4.7μF. C
TRAN
must be placed close to the transformer’s
primary winding connection and the IC local ground.
The capacitance should range between 47μF and 100μF.
Simple mode should have V
SNS
, V
CELL
, and D
CHRG
shorted
to V
IN
, which provides an excellent landing for both the
transformer primary and a single bypass cap (see the
Recommended Layout section). C
VIN
may be omitted in
Simple Mode provided that the C
TRAN
capacitor is in close
proximity to the V
IN
pin. C
VCELL
is used for bulk capacitance
and should be place close to the battery input connection.
Ceramic
capacitors are a good choice for bypassing due
to their moderate density, low internal series impedance,
and very low leakage current. Note that capacitor leak
-
age current at a given operating voltage goes down with
increasing
capacitor voltage rating. Ceramic capacitors
offer the lowest leakage current, while most electrolytic
capacitors are quite leaky.
Table 4. Recommended Output Diodes
MANUFACTURER
RECOMMENDED TRANSFORMER
TURNS RATIO (N) RANGE PART NUMBER I
F(AVG)
(A)
V
RRM
(V) t
rr
(ns)
JUNCTION
CAPACITANCE (pF) PACKAGE
STMicroelectronics 1 to 2 STPS3H100U 3 100 N/A 90 SMB
STPS2H100AY* 2 100 N/A 50 SMA
2 to 4 STTH102AY* 1 200 20 12 SMA
10 to 24 STTH112A 1 1200 75 SMA
Fairchild Semiconductor
www.fairchildsemi.com
1
to 2 ES2B 2
100 20 18 SMB
2 to 4 ES1D 1 200 15 7 SMA
4 to 8 ES1G 1 400 35 10 SMA
6 to 12 ES1J 1 600 35 8 SMA
Vishay
www.vishay.com
1
to 2 SS2H10*
2 100 N/A 70 SMB
U2B 2 100 20 16 SMB
2 to 4 ES1D 1 200 15 10 SMA
ES07D-M* 1.2 200 25 5 SMF
10 to 20 US1M 1 1000 50 10 SMA
*AEC-Q101 Qualified
LT8584
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Discharge Current Sense Resistor
The discharge current sense resistor, R
SNS
, should only
be used in serial mode. Omit this resistor and short V
SNS
and V
CELL
to V
IN
in simple mode. The maximum sense
voltage between V
VSNS
and V
VCELL
is 50mV. It is recom-
mended to design for a nominal sense voltage of 30mV. It
is
not recommended to design for a nominal sense voltage
below 20mV since the input offset voltage of the differential
amplifier contributes more error at the lower range.
R
SNS
=
V
VCELL
V
VSNS
I
DIS,AV
=
30mV
2.5A
= 12m
The internal amplifier amplifies the voltage difference
between V
VSNS
and V
VCELL
20× when V
IN
is tied to V
SNS
.
The voltage is referenced from V
CELL
such that:
V
VCELL
– V
OUT
= 20 • (R
SNS
I
DIS,AV
)
The measurement is the average discharge current, I
DIS,AV
,
and not the RMS value. The output, V
VIN
V
OUT
, is clamped
to a maximum of 1V.
Decode Window Resistor, R
RTMR
RTMR pin is used to set the duration of the decode window
and is programmed by selecting the value of the resis
-
tor connected between RTMR and GND. This pin is used
in serial mode only. Ground this pin when using simple
mode. The decode window is programmable from 1.9ms
to 31ms. Set the decode window duration 30% longer
than the required time to set the LT8584 in MODE 4 and
read back the handshake voltage. This allows the system
to detect if there is a communication error. Set R
RTMR
based on following equation:
R
RTMR
(kΩ) = 0.015 • t
2
W
+ 5.9 • t
W
– 1.1
where R
RTMR
is given in kΩ and t
W
is given in ms.
The RTMR pin is driven to 1.22V approximatelys after
the part is first enabled. This indicates the
decode window
is
active. The RTMR pin is taken low after the decode
window expires. The internal decoder states are latched
on the falling edge of RTMR (see Figure 4). The OUT pin
multiplexer then selects the correct input corresponding
to the programmed mode (refer to Table 1).
OUT Pin Compensation and Filtering
The OUT pin must have external compensation, C
OUT
, for
all applications including both serial mode and simple
mode. The external capacitor also provides necessary
filtering for the input to the BSM. The OUT amplifier is
internally compensated to handle capacitance ranging from
20nF to 220nF. Use 47nF for most applications to yield
approximately 100µs 1% settling time. A faster amplifier
response can be achieved by adding a zero using a resis
-
tor in
series with the external filter capacitor. Use 4.7nF
capacitor
with a 60Ω series resistor to achieve a sub-100µs
settling time. Note that in serial mode, the capacitors are
placed between adjacent LT8584 OUT pins. This effectively
doubles the compensation capacitance from the capacitor
value used. The OUT amplifier also has internal filtering
to both improve PSRR and handle large-signal steps or
spikes that may be present on the supply lines.
Additional filtering may be required
in noisy
environments.
Figure 10 shows a two-pole filter with the LT8584 operat-
ing in
serial mode. The resistors must be kept small to
minimize
error due to non-zero input currents into the
BSM. The LTC6804 is guaranteed to haveA or less
input bias current during measurement. There are two
resistors in any given measurement path. Thus, a 50Ω
series resistor will introduce up to a 200µV error. D
IN
pin
current will also cause an error when enabling a particular
LT8584, but the error term is canceled when making dif
-
ferential measurements.
8584 F10
OUT
AMP
LT8584
OUT
50Ω
C
OUT
47nF
100nF
OUT
AMP
LT8584
OUT
50Ω
C
OUT
47nF
100nF
TO BSM
±2µA
FROM BSM
C
OUT
47nF
100nF
±2µA
Figure 10. Optional OUT Pin Filtering
LT8584
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HOT SWAP™ PROTECTION
Large currents are developed when hot swapping a bat-
tery with
a LT8584 application due to the large input bulk
capacitance
coupled with the low ESR of the batteries. In
most cases, the LT8584 should have no problem handling
the overshoot voltage that follows the large inrush current.
The downstream BSM, however, might encounter damage
that requires additional steps and/or circuitry to protect
against hot swapping. Several solutions use a two-path
method incorporating a pre-charge resistive path and a
shunt path (see Figure 11).
This method has the disadvantage of lower efficiency and
higher cost. Use FETs for M1 in Figure 12 that have low
R
DS,ON
to maximize converter efficiency and have less than
a 1.25V V
GS
threshold. Table 7 lists several recommended
FETs for M1. C1 should be sized such that C1 ≥ C
VIN
/500.
The third active solution protects the flyback output capaci-
tors. All
flyback outputs sum together and flow through
D13.
During a Hot Swap condition, D13 will reverse bias
and prevent a large inrush current into the flyback output
capacitors. The peak repetitive reverse voltage, V
RRM
,
should exceed the maximum module voltage, V
MODULE
.
Several recommended diodes for D13 are given in Table 8.
Mechanical Solution
A
mechanical approach may result in a more cost effective
solution. A 10Ω resistor is used to pre-charge the C
VIN
capacitor to the battery voltage, limiting the inrush cur-
rent. After
the C
VIN
cap is charged, a mechanical short is
connected across the resistor and remains there during
all normal operations. There are three recommended solu
-
tions for the mechanical short: 1.) use a > 3A rated jumper
2.) use a mechanical switch or 3.) use a staggered-pin
battery connector. The staggered pin connection has the
long pins connecting to LT8584 through the 10Ω resistor.
The short pins connect directly to the LT8584, shorting
out the 10Ω resistor. Normal insertion has a delay on the
order of milliseconds between the long pin connecting
and short pin connecting to the circuit, allowing C
VIN
to
charge up through a current limiting resistor before the
mechanical short is made.
Order of Assembly
The order of assembly of the battery stack, the LT8584
balancers, and the BSM can also mitigate hot swapping
issues. Having separate boards for both the LT8584
balancers and the BSM is recommended. This allows the
LT8584 balancers to be built and connected during the
battery
stack assembly. The last step involves mating the
battery stack and LT8584 assembly with the BSM board.
Additional filters on the inputs into the BSM also reduce
possible issues during final assembly, see the OUT Pin
Compensation and Filtering section for more detail.
8584 F11
C
VIN
V
BAT
BATTERY
CONNECTION
+
10Ω
LT8584
D
IN
Figure 11. Dual Path Hot Swap Solution
For most applications, use the recommended Hot Swap
Solution shown as Active Solution 1 in Figure 12 and in
the Typical Application Section. Several other mechanical,
active, and order-of-assembly solutions are also given as
alternatives or as supplements.
Active Solution
An active solution has the added advantage of automatic
hot swap protection; no additional steps are needed when
connecting batteries. Tw o input protection solutions are
shown with the first solution using only TVS diodes. D1
is selected to trigger around 6V and to take the brunt of
the connection input pulse. The reverse leakage current
is more significant in low-voltage TVS’s. Table 5 gives
several diodes for D1 that have adequate current and
voltage characteristics while minimizing reverse leakage
current. D2 provides secondary protection for the BSM
inputs. These should be smaller than D1 since the LT8584’s
OUT pin limits current. Table 6 gives several diodes that
are optimal for D2.
The second active solution has additional overvoltage
protection via a fuse, F1, and a pre-charge MOSFET circuit.

LT8584IFE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management 2.5A Mono Active Cell Balancer w/ Teleme
Lifecycle:
New from this manufacturer.
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