GTLP18T612MEAX Datasheet GTLP18T612MTDX, GTLP18T612MTD, GTLP18T612MEAX | P1-P3

May 1999

Revised July 2002

GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver

GTLP18T612

18-Bit LVTTL/GTLP Universal Bus Transceiver

General Description

The GTLP18T612 is an 18-bit universal bus transceiver

which provides LVTTL to GTLP signal level translation. It

allows for transparent, latched and clocked modes of data

transfer. The device provides a high speed interface for

cards operating at LVTTL logic levels and a backplane

operating at GTLP logic levels. High speed backplane

operation is a direct result of GTLP’s reduced output swing

(

< 1V), reduced input threshold levels and output edge rate

control. The edge rate control minimizes bus settling time.

GTLP is a Fairchild Semiconductor derivative of the Gun-

ning Transistor logic (GTL) JEDEC standard JESD8-3.

Fairchild’s GTLP has internal edge-rate control and is Pro-

cess, Voltage, and Temperature (PVT) compensated. Its

function is similar to BTL or GTL but with different output

levels and receiver thresholds. GTLP output LOW level is

less than 0.5V, the output HIGH is 1.5V and the receiver

threshold is 1.0V.

Features

■ Bidirectional interface between GTLP and LVTTL logic

levels

■ Designed with edge rate control circuitry to reduce out-

put noise on the GTLP port

■ V

REF

pin provides external supply reference voltage for

receiver threshold adjustibility

■ Special PVT compensation circuitry to provide consis-

tent performance over variations of process, supply volt-

age and temperature

■ TTL compatible driver and control inputs

■ Designed using Fairchild advanced BiCMOS technology

■ Bushold data inputs on A port to eliminate the need for

external pull-up resistors for unused inputs

■ Power up/down and power off high impedance for live

insertion

■ Open drain on GTLP to support wired-or connection

■ Flow through pinout optimizes PCB layout

■ D-type flip-flop, latch and transparent data paths

■ A Port source/sink

−24mA/+24mA

■ B Port sink

+50mA

■ Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Ordering Code:

Note 1: Ordering code “G” indicates Trays.

Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Order Number Package Number Package Description

GTLP18T612G

(Note 1)(Note 2)

BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

GTLP18T612MEA

(Note 2)

MS56A

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

GTLP18T612MTD

(Note 2)

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

www.fairchildsemi.com 2

GTLP18T612

Connection Diagrams

Pin Assignments for SSOP and TSSOP

Pin Assignments for FBGA

(Top Thru View)

Pin Descriptions

FBGA Pin Assignments

Pin Names Description

OEAB

A-to-B Output Enable

(Active LOW) (LVTTL Level)

OEBA

B-to-A Output Enable

(Active LOW) (LVTTL Level)

CEAB

A-to-B Clock/LE Enable

(Active LOW) (LVTTL Level)

CEBA

B-to-A Clock/LE Enable

(Active LOW) (LVTTL Level)

LEAB A-to-B Latch Enable

(Transparent HIGH) (LVTTL Level)

LEBA B-to-A Latch Enable

(Transparent HIGH) (LVTTL Level)

REF

GTLP Input Threshold

Reference Voltage

CLKAB A-to-B Clock (LVTTL Level)

CLKBA B-to-A Clock (LVTTL Level)

A1–A18 A-to-B Data Inputs or

B-to-A 3-STATE Outputs

B1–B18 B-to-A Data Inputs or

A-to-B Open Drain Outputs

123456

A A

OEAB CLKAB B

B A

LEAB CEAB B

C A

D A

GND GND B

E A

GND GND B

F A

GND GND B

G A

REF

H A

OEBA CEBA B

J A

LEBA CLKBA B

3 www.fairchildsemi.com

GTLP18T612

Functional Description

The GTLP18T612 is an 18 bit registered transceiver con-

taining D-type flip-flop, latch and transparent modes of

operation for the data path. Data flow in each direction is

controlled by the clock enables (CEAB

and CEBA), latch

enables (LEAB and LEBA), clock (CLKAB and CLKBA)

and output enables (OEAB

and OEBA). The clock enables

(CEAB

and CEBA) and the output enables (OEAB and

OEBA

) control the 18 bits of data for the A-to-B and B-to-A

directions respectively.

For A-to-B data flow, when CEAB

is LOW, the device oper-

ates on the LOW-to-HIGH transition of CLKAB for the flip-

flop and on the HIGH-to-LOW transition of LEAB for the

latch path. That is, if CEAB

is LOW and LEAB is LOW the

A data is latched regardless as to the state of CLKAB

(HIGH or LOW) and if LEAB is HIGH the device is in trans-

parent mode. When OEAB

is LOW the outputs are active.

When OEAB

is HIGH the outputs are HIGH impedance.

The data flow of B-to-A is similar except that CEBA

, OEBA,

LEBA, and CLKBA are used.

Truth Table

(Note 3)

Note 3: A-to-B data flow is shown. B-to-A data flow is similar but uses

OEBA

, LEBA, CLKBA, and CEBA.

Note 4: Output level before the indicated steady state input conditions were

established, provided that CLKAB was HIGH before LEAB went LOW.

Note 5: Output level before the indicated steady-state input conditions

were established.

Logic Diagram

Inputs Output Mode

CEAB

OEAB LEAB CLKAB A B

X H X X X Z Latched

LLL HXB

(Note 4) Storage

LLL LXB

(Note 5) of A Data

X L H X L L Transparent

XLH XHH

LLL

↑ L L Clocked

LLL

↑ HH Storage

of A Data

HLL XXB

(Note 5) Clock Inhibit

P1-P3 P4-P6 P7-P9 P10-P10

GTLP18T612MEAX

Mfr. #:

Buy GTLP18T612MEAX

Manufacturer:

ON Semiconductor / Fairchild

Description:

Bus Transceivers 18-Bit Univ Bus Tran

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

GTLP18T612MEAX

GTLP18T612MEAX

Products related to this Datasheet