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89HPES6T5ZBBC8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
1 of 28 June 18, 2014
2014 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
®
Device Overview
The 89HPES6T5 is a member of IDT’s PRECISE™ family of PCI
Express switching solutions. The PES6T5 is an 6-lane, 5-port peripheral
chip that performs PCI Express Base switching. It provides connectivity
and switching functions between a PCI Express upstream port and up to
four downstream ports and supports switching between downstream
ports.
Features
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High Performance PCI Express Switch
– Six 2.5Gbps PCI Express lanes
– Five switch ports
– Upstream port is x2
– Downstream ports are x1
– Low-latency cut-through switch architecture
– Support for Max Payload Sizes up to 256 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
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Flexible Architecture with Numerous Configuration Options
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Ability to load device configuration from serial EEPROM
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Legacy Support
– PCI compatible INTx emulation
– Bus locking
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Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates six 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
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Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
boards
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Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Support PCI Power Management Interface specification (PCI-
PM 1.2)
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
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Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Block Diagram
Figure 1 Internal Block Diagram
5-Port Switch Core / 6 PCI Express Lanes
Frame Buffer Route Table
Port
Arbitration
Scheduler
SerDes
Phy
Logical
Layer
Mux / Demux
Transaction Layer
Data Link Layer
(Port 0)
(Port 2)
SerDes
Phy
Logical
Layer
Mux / Demux
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
Mux / Demux
Transaction Layer
Data Link Layer
(Port 3)
(Port 5)
SerDes
Phy
Logical
Layer
Transaction Layer
Data Link Layer
Mux / Demux
(Port 4)
SerDes
Phy
Logical
Layer
Transaction Layer
Data Link Layer
Mux / Demux
SerDes
Phy
Logical
Layer
89HPES6T5
Data Sheet
6-Lane 5-Port
PCI Express® Switch
2 of 28 June 18, 2014
IDT 89HPES6T5 Data Sheet
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11 General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
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Packaged in a 15mm x 15mm 196-ball BGA with 1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES6T5 provides the most efficient I/O connectivity solution for applications requiring high
throughput, low latency, and simple board layout with a minimum number of board layers. It provides 3 GBps (24 Gbps) of aggregated, full-duplex
switching capacity through 6 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both direc-
tions and is fully compliant with PCI Express Base specification revision 1.1.
The PES6T5 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transac-
tion layers in compliance with PCI Express Base specification Revision 1.1. The PES6T5 can operate either as a store and forward or cut-through
switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated
resource management to allow efficient switching for applications requiring additional narrow port connectivity.
Figure 2 I/O Expansion Application
SMBus Interface
The PES6T5 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES6T5, allowing every
configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of
the PES6T5 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an
external Hot-Plug I/O expander.
Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In
the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these
address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up
on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in
Table 1.
Memory
Memory
Memory
Processor
Memory
North
Bridge
PES6T5
Processor
x1
x1
x1
x1
South
Bridge
GE
LOM
x2
GE
LOM
GE
1394
3 of 28 June 18, 2014
IDT 89HPES6T5 Data Sheet
As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure
3(a), the master and slave SMBuses are tied together and the PES6T5 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES6T5 registers supports SMBus arbitration. In some systems, this SMBus master
interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support
these systems, the PES6T5 may be configured to operate in a split configuration as shown in Figure 3(b).
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
The PES6T5 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the
serial EEPROM.
Figure 3 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES6T5 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES6T5 utilizes
an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, when-
ever the state of a Hot-Plug output needs to be modified, the PES6T5 generates an SMBus transaction to the I/O expander with the new value of all of
the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate
function of GPIO) of the PES6T5. In response to an I/O expander interrupt, the PES6T5 generates an SMBus transaction to read the state of all of the
Hot-Plug inputs from the I/O expander.
Bit
Slave
SMBus
Address
Master
SMBus
Address
1 SSMBADDR[1] MSMBADDR[1]
2 SSMBADDR[2] MSMBADDR[2]
3 SSMBADDR[3] MSMBADDR[3]
4 0 MSMBADDR[4]
5 SSMBADDR[5] 1
61 0
71 1
Table 1 Master and Slave SMBus Address Assignment
Processor
PES6T5
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
Processor
PES6T5
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
...
...
(a) Unified Configuration and Management Bus
(b) Split Configuration and Management Buses
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89HPES6T5ZBBC8

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Buy 89HPES6T5ZBBC8
Manufacturer:
IDT
Description:
PCI Interface IC PCI EXPRESS SWITCH
Lifecycle:
New from this manufacturer.
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