89HPES6T5ZBBC8 Datasheet 89HPES6T5ZBBCG8, 89HPES6T5ZBBCGI, 89HPES6T5ZBBCG | P4-P6

4 of 28 June 18, 2014

IDT 89HPES6T5 Data Sheet

General Purpose Input/Output

The PES6T5 provides 11 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may

be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These alternate

functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.

Pin Description

The following tables lists the functions of the pins provided on the PES6T5. Some of the functions listed may be multiplexed onto the same pin. The

active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level.

All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.

Signal Type Name/Description

PE0RP[1:0]

PE0RN[1:0]

I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive

pairs for port 0.

PE0TP[1:0]

PE0TN[1:0]

O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 0.

PE2RP[0]

PE2RN[0]

I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive

pair for port 2.

PE2TP[0]

PE2TN[0]

O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-

mit pair for port 2.

PE3RP[0]

PE3RN[0]

I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive

pair for port 3.

PE3TP[0]

PE3TN[0]

O PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-

mit pair for port 3.

PE4RP[0]

PE4RN[0]

I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive

pair for port 4.

PE4TP[0]

PE4TN[0]

O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-

mit pair for port 4.

PE5RP[0]

PE5RN[0]

I PCI Express Port 5 Serial Data Receive. Differential PCI Express receive

pair for port 5.

PE5TP[0]

PE5TN[0]

O PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans-

mit pair for port 5.

PEREFCLKP

PEREFCLKN

I PCI Express Reference Clock. Differential reference clock pair input. This

clock is used as the reference clock by on-chip PLLs to generate the clocks

required for the system logic and on-chip SerDes. The frequency of the dif-

ferential reference clock is determined by the REFCLKM signal.

REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the fre-

quency of the reference clock input.

0x0 - 100 MHz

0x1 - 125 MHz

Table 2 PCI Express Interface Pins

5 of 28 June 18, 2014

IDT 89HPES6T5 Data Sheet

Signal Type Name/Description

MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the

serial EEPROM from which configuration information is loaded.

MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize

transfers on the master SMBus.

MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-

ter SMBus.

SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to

which the slave SMBus interface responds.

SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-

fers on the slave SMBus.

SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave

SMBus.

Table 3 SMBus Interface Pins

Signal Type Name/Description

GPIO[0] I/O General Purpose I/O.