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IS62LV256-70UI-TR

P1-P3P4-P6P7-P9
IS62LV256 ISSI
®
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. K
12/11/02
CAPACITANCE
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 5 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vcc =3.3V.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-45 ns -70 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
I
CC1 Vcc Operating VCC = Max., CE = VIL Com. — 20 — 20 mA
Supply Current IOUT = 0 mA, f = 0 Ind. — 30 — 30
ICC2 Vcc Dynamic Operating VCC = Max., CE = VIL Com. — 35 — 30 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 45 — 40
ISB1 TTL Standby Current VCC = Max., Com. — 2 — 2 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 5 — 5
CE
≥
VIH, f = 0
ISB2 CMOS Standby VCC = Max., Com. — 90 — 90 µA
Current (CMOS Inputs) CE
≥
VCC – 0.2V, Ind. — 200 — 200
VIN
≥
VCC – 0.2V, or
VIN
≤
0.2V, f = 0
Notes:
1. At f = f
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS62LV256 ISSI
®
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
5
Rev. K
12/11/02
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-45 ns -70 ns
Symbol Parameter Min. Max. Min. Max. Unit
tRC Read Cycle Time 45 — 70 — ns
tAA Address Access Time — 45 — 70 ns
tOHA Output Hold Time 2 — 2 — ns
tACE CE Access Time — 45 — 70 ns
tDOE OE Access Time — 25 — 35 ns
tLZOE
(2)
OE to Low-Z Output 0 — 0 — ns
tHZOE
(2)
OE to High-Z Output 0 20 0 25 ns
tLZCE
(2)
CE to Low-Z Output 3 — 3 — ns
tHZCE
(2)
CE to High-Z Output 0 20 0 25 ns
tPU
(3)
CE to Power-Up 0 — 0 — ns
tPD
(3)
CE to Power-Down — 30 — 50 ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 5 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1a and 1b
1213 Ω
100 pF
Including
jig and
scope
1378 Ω
OUTPUT
3.3V
1213 Ω
5 pF
Including
jig and
scope
1378 Ω
OUTPUT
3.3V
Figures 1a
Figures 1b
IS62LV256 ISSI
®
6
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. K
12/11/02
50%50%
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
t
PD
HIGH-Z
t
PU
DATA VALID
t
HZCE
ISB
ADDRESS
OE
CE
D
OUT
SUPPLY
CURRENT
ICC
HIGH-Z
READ CYCLE NO. 2
(1,3)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = V
IL.
3. Address is valid prior to or coincident with CE LOW transitions.
DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
P1-P3P4-P6P7-P9

IS62LV256-70UI-TR

Mfr. #:
Buy IS62LV256-70UI-TR
Manufacturer:
ISSI
Description:
SRAM 256K 32Kx8 70ns 3.3v
Lifecycle:
New from this manufacturer.
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