1. General description
The 74LVCH322245A is a 32-bit transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. The device features four output
enable (nOE) inputs for easy cascading and four send/receive (nDIR) inputs for direction
control. Pin nOE controls the outputs so that the buses are effectively isolated. The device
is designed with 30 Ω series termination resistors in both HIGH and LOW output stages to
reduce line noise.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed
3.3 V and 5 V applications.
To ensure the high-impedance state during power-up or power-down, pin nOE should be
tied to V
CC
through a pull-up resistor; the minimum value of the resistor is determined by
the current-sinking capability of the driver.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused
inputs.
2. Features
n 5 V tolerant inputs/outputs for interfacing with 5 V logic
n Wide supply voltage range from 1.2 V to 3.6 V
n CMOS low power consumption
n MULTIBYTE flow-through standard pin-out architecture
n Low inductance multiple power and ground pins for minimum noise and ground
bounce
n Direct interface with TTL levels
n Inputs accept voltages up to 5.5 V
n All data inputs have bus hold
n Integrated 30 Ω termination resistors
n Complies with JEDEC standard JESD8-B / JESD36
n ESD protection:
u HBM EIA/JESD22-A114-B exceeds 2000 V
u MM EIA/JESD22-A115-A exceeds 200 V
n Specified from −40 °Cto+85°C
n Packaged in plastic fine-pitch ball grid array package
74LVCH322245A
32-bit bus transceiver with direction pin; 30 Ω series
temination resistors; 5 V tolerant; 3-state
Rev. 03 — 20 August 2007 Product data sheet
