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74LVCH322245AEC,51

P1-P3P4-P6P7-P9P10-P12P13-P13
74LVCH322245A_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 20 August 2007 4 of 13
NXP Semiconductors
74LVCH322245A
32-bit bus transceiver with direction pin, 30 Ω resistors
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 2. Bus hold circuit
mna473
V
CC
data
input
to internal circuit
Fig 3. Pin configuration
mna475
1A1 1A3 1A5 1A7 2A1 2A3 2A5 2A6 3A1 3A3 3A5 3A7 4A1 4A3 4A5 4A6
1A0 1A2 1A4 1A6 2A0 2A2 2A4 2A7 3A0 3A2 3A4 3A6 4A0 4A2 4A4 4A7
1B0 1B2 1B4 1B6 2B0 2B2 2B4 2B7 3B0 3B2 3B4 3B6 4B0 4B2 4B4 4B7
1B1 1B3 1B5 1B7 2B1 2B3 2B5 2B6 3B1 3B3 3B5 3B7 4B1 4B3 4B5 4B6
1OE 2OE 3OEGND GND GND GND 4OEV
CC
V
CC
GND GND GND GNDV
CC
V
CC
1DIR
6
5
2
1
4
3 2DIR 3DIRGND GND GND GND 4DIRV
CC
V
CC
GND GND GND GNDV
CC
V
CC
AHJBDEG TCF KMNRLP
Table 2. Pin description
Pin name Ball Description
nDIR (n = 1 to 4) A3, H3, J3, T3 direction control
n
OE (n = 1 to 4) A4, H4, J4, T4 output enable input (active LOW)
1A[0:7] A5, A6, B5, B6, C5, C6, D5, D6 input or output
1B[0:7] A2, A1, B2, B1, C2, C1, D2, D1 input or output
2A[0:7] E5, E6, F5, F6, G5, G6, H6, H5 input or output
2B[0:7] E2, E1, F2, F1, G2, G1, H1, H2 input or output
3A[0:7] J5, J6, K5, K6, L5, L6, M5, M6 input or output
3B[0:7] J2, J1, K2, K1, L2, L1, M2, M1 input or output
4A[0:7] N5, N6, P5, P6, R5, R6, T6, T5 input or output
4B[0:7] N2, N1, P2, P1, R2, R1, T1, T2 input or output
GND B3, B4, D3, D4, E3, E4, G3, G4, K3, K4,
M3, M4, N3, N4, R3, R4
ground (0 V)
V
CC
C3, C4, F3, F4, L3, L4, P3, P4 supply voltage
74LVCH322245A_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 20 August 2007 5 of 13
NXP Semiconductors
74LVCH322245A
32-bit bus transceiver with direction pin, 30 Ω resistors
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] All supply and ground pins connected externally to one voltage source.
[4] Above 70 °C the value of P
tot
derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 3. Function selection
[1]
Input Output
nOE nDIR nAn nBn
L L A = B inputs
L H inputs B = A
HXZZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage −0.5 +6.5 V
I
IK
input clamping current V
I
<0V −50 - mA
V
I
input voltage
[1]
−0.5 +6.5 V
I
OK
output clamping current V
O
>V
CC
or V
O
<0V - ±50 mA
V
O
output voltage output HIGH or LOW state
[2]
−0.5 V
CC
+ 0.5 V
output 3-state
[2]
−0.5 +6.5 V
I
O
output current V
O
= 0 V to V
CC
- ±50 mA
I
CC
supply current
[3]
- 200 mA
I
GND
ground current
[3]
−200 - mA
T
stg
storage temperature −65 +150 °C
P
tot
total power dissipation T
amb
= −40 °C to +85 °C
[4]
- 1000 mW
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
CC
supply voltage for maximum speed performance 2.7 - 3.6 V
for low-voltage applications 1.2 - - V
V
I
input voltage 0 - 5.5 V
V
O
output voltage output HIGH or LOW state 0 - V
CC
V
output 3-state 0 - 5.5 V
T
amb
ambient temperature in free air −40 - +85 °C
∆t/∆V input transition rise and fall
rate
V
CC
= 1.2 V to 2.7 V - - 20 ns/V
V
CC
= 2.7 V to 3.6 V - - 10 ns/V
74LVCH322245A_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 20 August 2007 6 of 13
NXP Semiconductors
74LVCH322245A
32-bit bus transceiver with direction pin, 30 Ω resistors
9. Static characteristics
[1] All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
=25°C.
[2] The bus hold circuit is switched off when V
I
>V
CC
allowing 5.5 V on the input terminal.
[3] For I/O ports the parameter I
OZ
includes the input leakage current.
[4] Valid for data inputs only. Note that control inputs do not have a bus hold circuit.
[5] The specified sustaining current at the data input holds the input below the specified V
I
level.
[6] The specified overdrive current at the data input forces the data input to the opposite input state.
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions V
CC
(V) Min Typ
[1]
Max Unit
T
amb
= −40 °C to +85 °C
V
IH
HIGH-level input voltage 1.2 V
CC
--V
2.7 to 3.6 2.0 - - V
V
IL
LOW-level input voltage 1.2 - - GND V
2.7 to 3.6 - - 0.8 V
V
OH
HIGH-level output voltage V
I
=V
IH
or V
IL
I
O
= −100 µA 2.7 to 3.6 V
CC
− 0.2 V
CC
-V
I
O
= −6 mA 2.7 V
CC
− 0.5 - - V
I
O
= −12 mA 3.0 V
CC
− 0.8 - - V
V
OL
LOW-level output voltage V
I
=V
IH
or V
IL
I
O
= 100 µA 2.7 to 3.6 - 0 0.20 V
I
O
= 6 mA 2.7 - - 0.40 V
I
O
= 12 mA 3.0 - - 0.55 V
I
I
input leakage current V
I
= 5.5 V or GND 3.6
[2]
- ±0.1 ±5 µA
I
OZ
OFF-state output current V
I
=V
IH
or V
IL
;
V
O
= 5.5 V or GND
3.6
[2][3]
- ±0.1 ±5 µA
I
OFF
power-off leakage current V
I
or V
O
= 5.5 V 0.0 - ±0.1 ±10 µA
I
CC
supply current V
I
=V
CC
or GND; I
O
= 0 A 3.6 - 0.1 40 µA
∆I
CC
additional supply current per input pin;
V
I
=V
CC
− 0.6 V; I
O
=0A
2.7 to 3.6 - 5 500 µA
C
I
input capacitance V
I
= GND to V
CC
0 to 3.6 - 5.0 - pF
C
I/O
input/output capacitance V
I
= GND to V
CC
0 to 3.6 - 10 - pF
I
BHL
bus hold LOW current V
I
= 0.8 V 3.0
[4][5]
75 - - µA
I
BHH
bus hold HIGH current V
I
= 2.0 V 3.0
[4][5]
−75 - - µA
I
BHLO
bus hold LOW overdrive
current
3.6
[4][6]
500 - - µA
I
BHHO
bus hold HIGH overdrive
current
3.6
[4][6]
−500 - - µA
P1-P3P4-P6P7-P9P10-P12P13-P13

74LVCH322245AEC,51

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Manufacturer:
NXP Semiconductors
Description:
IC TXRX NON-INVERT 3.6V 96LFBGA 74LVCH
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