LT4276
10
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Inrush and Powered On
Once the PSE detects and optionally classifies the PD, the
PSE then powers on the PD. When the port voltage rises
above the V
HSON
threshold, it begins to source I
GPU
out
of the HSGATE pin. This current flows into an external
capacitor (C
GATE
in Figure 5) that causes a voltage to ramp
up the gate of the external MOSFET. The external MOSFET
acts as a source follower and ramps the voltage up on
the output bulk capacitor (C
PORT
in Figure 5), thereby
determining the inrush current (I
INRUSH
in Figure 5). To
meet IEEE requirements, design I
INRUSH
to be ~100mA.
The LT4276 internal charge pump provides an N-channel
MOSFET solution, eliminating a larger and more costly
P-channel FET. The low R
DS(ON)
MOSFET also maximizes
power delivery and efficiency, reduces power and heat
dissipation, and eases thermal design.
Figure 5. Programming I
INRUSH
Figure 6. V
CC
Buck Regulator
EXTERNAL V
CC
SUPPLY
The external V
CC
supply must be configured as a buck
regulator shown in Figure 6. To optimize the buck regulator,
use the external component values in Table 2 correspond
-
ing to the V
IN
operating range. This buck regulator runs
in discontinuous mode with the inductor peak current
considerably higher than average load current on V
CC
.
Thus, the saturation current rating of the inductor must
exceed the values shown in Table 2. Place the capacitor, C,
as close as possible to V
CC
pin 21 and GND pin 19. For
optimal performance, place the external components as
close as possible to the LT4276.
LT4276
HSGATE
GND
4276 F05
VPORT HSSRC
C
GATE
I
GPU
3.3k
+
C
PORT
VPORT
I
INRUSH
I
INRUSH
=I
GPU
C
PORT
C
GATE
DELAY START
After the HSGATE charges up to approximately 7V above
HSSRC, fully enhancing the external Hot Swap MOSFET,
the switching regulator controller operates after a delay
of t
START
. During this delay, the LT4276 draws I
MPS
from
VPORT to ensure that the PSE does not DC disconnect
the PD due to Maintain Power Signature requirements.
V
IN
R
e
V
CC
V
IN
V
CC
GND
SWVCC
LT4276
FMMT723
PBSS9110T
L(µH)
C(µF)
4276 F06
AUXILIARY SUPPLY OVERRIDE
If the AUX pin is held above V
AUXT
, the LT4276 enters
auxiliary power supply override mode. In this mode the
signature resistor is disconnected, classification is dis
-
abled, and HSGATE is pulled down. The T2P pin pulls up
to V
CC
on the LT4276B (or the LT4276A when no R
CLS
++
resistor is present). The T2P pin alternates between pulling
up and floating at f
T2P
on the LT4276A when the R
CLS
++
resistor is present.
The AUX pin allows for setting the auxiliary supply turn on
(V
AUXON
) and turn off (V
AUXOFF
) voltage thresholds. The
auxiliary supply hysteresis voltage (V
AUXHYS
) is set by
sinking current (I
AUXH
) only when the AUX pin voltage is
Table 2 . Buck Regulator Component Selection
V
IN
C L I
SAT
R
e
9V-57V
PoE
22µF
10µF
22µH
100µH
≥1.2A
≥300mA
20Ω
LT4276
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Figure 7. AUX Threshold and Hysteresis Calculation
LT4276
GND
4276 F08a
AUX
R1
V
AUX
+
R2
R1=
V
AUXON
V
AUXOFF
I
AUXH
=
V
AUXHYS
I
AUXH
R2 =
R1
V
AUXOFF
V
AUXT
1
R1
V
AUX(MAX)
V
AUXT
1.4mA
SWITCHING REGULATOR CONTROLLER OPERATION
The switching regulator controller portion of the LT4276
is a current mode controller capable of implementing
either a flyback or a forward power supply. When used in
flyback mode, no opto-isolator is required for feedback
because the output voltage is sensed via the transformer’s
third winding.
Flyback Mode
The LT4276 is programmed into flyback mode by placing
a resistor R
FFSDLY
from the FFSDLY pin to GND. This resis-
tor must be in the range of 5.23kΩ to 52.3kΩ. If using a
potentiometer to adjust R
FFSDLY
, ensure the adjustment
of the potentiometer does not exceed 52.3kΩ.The value
of R
FFSDLY
determines t
PGDELAY
according to the following
equations:
t
PGDELAY
2.69ns /kΩ R
FFSDLY
+ 30ns
t
PGSG
20ns
The PG and SG relationships in flyback mode are shown
in Figure 8.
The SG pin must be connected to the secondary side
MOSFET through a gate drive transformer as shown in
Figure 9. Add a Schottky diode from PG to GND as shown
in Figure 9 to prevent PG from going negative.
Figure 8: PG and SG Relationship in Flyback Mode
Figure 9: Example PG and SG Connections in Flyback Mode
PG
SG
4276 F07
t
PGDELAY
t
PGon
t
PGSG
PG
SGGND
LT4276
4276 F08
FFSDLY
R
FFSDLY
ISEN
+
ISEN
+
Forward Mode
The LT4276 is programmed into forward mode by placing
a resistor R
FFSDLY
from the FFSDLY pin to V
CC
. The R
FFSDLY
resistor must be in the range of 10.5kΩ to 52.3kΩ. If using
a potentiometer to adjust R
FFSDLY
ensure the adjustment
of the potentiometer does not exceed 52.3kΩ.
The value of R
FFSDLY
determines t
PGDELAY
and t
PGSG
ac-
cording to the following equations:
t
PGDELAY
≈ 7.16ns/kΩ R
FFSDLY
+ 17ns
t
PGSG
≈ 5.60ns/kΩ R
FFSDLY
+ 7.9ns
The PG and SG relationships in forward mode are shown
in Figure 10.
less than V
AUXT
. Use the following equations to set V
AUXON
and V
AUXOFF
via R1 and R2 in Figure 7. A capacitor up to
1000pF may be placed between the AUX pin and GND to
improve noise immunity.
V
AUXON
must be lower than V
HSOFF
.
LT4276
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Figure 10: PG and SG relationship in Forward Mode
In forward mode, the SG pin has the correct polarity to
drive the active clamp P-channel MOSFET through a simple
level shifter as shown in Figure 11. Add a Schottky diode
from the PG to GND as shown in Figure 11 to prevent PG
from going negative.
FEEDBACK AMPLIFIER
In the flyback mode, the feedback amplifier senses the
output voltage through the transformers third winding as
shown in Figure 12. The amplifier is enabled only during the
fixed interval, t
FB
, as shown in Figure 13. This eliminates
the opto-isolator in isolated designs, thus greatly improving
the dynamic response and stability over lifetime. Since t
FB
is a fixed interval, the time-averaged transconductance,
gm, varies as a function of the user-selected switching
frequency.
PG
SG
4276 F09
t
PGDELAY
t
PGSG
Figure 11: Example PG and SG Connections in Forward Mode
PG
V
CC
V
CC
SG
GND
LT4276
4276 F10
FFSDLY
R
FFSDLY
ISEN
+
ISEN
+
+
+
FEEDBACK
FB31
LT4276
THIRD
PRIMARY
4276 F11
SECONDARY
ITHB
PG
ISEN
+
ISEN
RLDCMP
R
FB2
V
IN
V
OUT
R
SENSE
V
FB
R
FB1
R
LDCMP
A
V
= 10
Figure 12: Feedback and Load Compensation Connection
Figure 13: Feedback Amplifier Timing Diagram
PG
FB31
VOLTAGE
GND
SG
4276 F09
t
FB
t
FBDLY
V
FB
FEEDBACK AMPLIFIER OUTPUT, ITHB
As shown in the Block Diagram, V
SENSE
is the input of
the Current Sense Comparator. V
SENSE
is derived from
the output of a linear amplifier whose input is the voltage
on the ITHB pin, V
ITHB
.
This linear amplifier inverts its input, V
ITHB
, with a gain,
ΔV
SENSE
/ΔV
ITHB
, and with an offset voltage of V
ITHB(OS)
to yield its output, V
SENSE
. This relationship is shown
graphically in Figure 1. Note the slope ΔV
SENSE
/ΔV
ITHB
is a negative number and is provided in the electrical
characteristics table.
V
ITHB
= V
ITHB(OS)
+ V
SENSE
ΔV
SENSE
ΔV
ITHB

LT4276BHUFD#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN PoE+ PD with Forward/Flyback Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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