LT4276
13
4276fa
For more information www.linear.com/LT4276
The block diagram shows V
SENSE
is compared against
the voltage across the current sense resistor, V(ISEN
+
)-
V(ISEN
) modified by the internal slope compensation
voltage discussed subsequently.
LOAD COMPENSATION
As can be seen in Figure 13, the voltage on the FB31 pin
droops slightly during the flyback period. This is mostly
caused by resistances of components of the secondary
side such as: the secondary winding, R
DS(ON)
of the syn-
chronous MOSFET, ESR of the output capacitor, etc. These
resistances cause a feedback error that is proportional to
the current in the secondary loop at the time of feedback
sample window
. To compensate for this error, the LT4276
places a voltage proportional to the peak current in the
primary winding on the RLDCMP pin.
Determining Feedback and Load Compensation
Resistors
Because the resistances of components on the secondary
side are generally not well known, an empirical method
must be used to determine the feedback and load com
-
pensation resistor values.
INITIALLY SET R
FB2
= 2kΩ
R
FB1
R
FB2
V
OUT
V
FB
N
THIRD
N
SECONDARY
R
FB2
Connect the resistor R
LDCMP
between the RLDCMP pin and
GND. R
LDCMP
must be at least 10kΩ. Adjust R
LDCMP
for
minimum change of V
OUT
over the full input and output load
range. A potentiometer in series with 10kΩ may be initially
used for R
LDCMP
and adjusted. The potentiometer+10kΩ
may then be removed, measured, and replaced with the
equivalent fixed resistor. The resulting V
OUT
differs from
the desired V
OUT
due to offset injected by load compensa-
tion. The change to R
FB2
to correct this is predicted by:
ΔR
FB2
=
ΔV
OUT
V
FB
N
THIRD
N
SECONDARY
R
FB2
2
R
FB1
applicaTions inForMaTion
Where: ΔV
OUT
is the desired change to V
OUT
ΔR
FB2
is the required change to R
FB2
N
THIRD
/N
SECONDARY
is the transformer third
winding to secondary winding
OPTO-ISOLATOR FEEDBACK
For forward mode operation, the flyback voltage cannot be
sensed across the transformer. Thus, opto-isolator feed
-
back must be used. When using opto-isolator feedback,
connect the
FB31
pin to GND and leave the RLDCMP pin
open. In this condition, the feedback amplifier sinks an
average current of I
SINK
into the ITHB pin. An example for
feedback connections is shown in Figure 14. Note that
since I
SINK
is time-averaged over the switching period,
the sink current varies as a function of the user-selected
switching frequency.
Figure 14: Opto-isolator Feedback
Connections in the Forward Mode
LT4276
ITHB
4276 F13
V
CC
V
OUT
C
X
R
X
FB31GND
SOFT-START
In PoE applications, a proper soft-start design is required
to prevent the PD from drawing more current than the
PSE can provide.
The soft-start time, t
SFST
, is approximately the time in
which the power supply output voltage, V
OUT
, is charg-
ing its output capacitance, C
OUT
. This results in an inrush
current at the port of the PD, Iport_inrush. Care must be
taken in selecting t
SFST
to prevent the PD from drawing
more current than the PSE can provide.
LT4276
14
4276fa
For more information www.linear.com/LT4276
applicaTions inForMaTion
In the absence of an output load current, the Iport_inrush,
is approximated by the following equation:
Iport_inrush ≈ (C
OUT
V
OUT
2
)/(η t
SFST
V
IN
)
where η is the power supply efficiency,
V
IN
is the input voltage of the PD
Iport_inrush plus the port current due to the load current
must be below the current the PSE can provide. Note that
the PSE current capability depends on the PSE operating
standard.
The LT4276 contains a soft-start function that controls
t
SFST
by connecting an external capacitor, C
SFST
, between
the SFST pin and GND. The SFST pin is pulled up with I
SFST
when the LT4276 begins switching. The voltage ramp on
the SFST pin is proportional to the duty cycle ramp for PG.
For flyback mode, the soft-start time is:
t
SFST
=
600µA
nF
C
SFST
I
SFST
t
PGon
+ t
PGDELAY
t
MIN
( )
where t
PGon
is the time when PG is high as shown in
Figure 8 once the power supply is in steady-state.
In for
ward mode, each of the back page applications sche-
matics provides a chart with t
SFST
vs. C
SFST
. Select the
application and choose a value of C
SFST
that corresponds
to the desired soft-start time.
CURRENT SENSE COMPARATOR
The LT4276 uses a differential current sense comparator
to reduce the effects of stray resistance and inductance
on the measurement of the primary current. ISEN
+
and
ISEN
must be Kelvin connected to the sense resistor pads.
Like most switching regulator controllers, the current
sense comparator begins sensing the current t
MIN
after
PG turns on. Then, the comparator turns PG off after the
voltage across ISEN
+
and ISEN exceeds the current
sense comparator threshold, V
SENSE
. Note that the voltage
across ISEN
+
and ISEN is modified by LT4276’s internal
slope compensation.
SLOPE COMPENSATION
The LT4276 incorporates current slope compensation.
Slope compensation is required to ensure current loop
stability when the duty cycle is greater than or near 50%.
The slope compensation of the LT4276 does not reduce
the maximum peak current at higher duty cycles.
CONTROL LOOP COMPENSATION
In flyback mode, loop frequency compensation is per
-
formed by connecting a resistor/capacitor network from
the output
of the feedback amplifier (ITHB pin) to GND as
shown in Figure 12. In forward mode, loop compensation
is performed by varying R
X
and C
X
in Figure 14.
ADJUSTABLE SWITCHING FREQUENCY
The LT4276 has a default switching frequency, f
OSC
, of 214
kHz when the ROSC pin is left open. If a higher switching
frequency, f
SW
, is desired (up to 300 kHz), a resistor no
smaller than 45.3kΩ may be added between the ROSC pin
to GND. The resistor can be calculated below:
R
OSC
=
3900kΩ kHz
f
SW
f
OSC
( )
kΩ
( )
SHORT CIRCUIT RESPONSE
If the power supply output voltage is shorted, overloaded,
or if the soft-start capacitor is too small, an overcurrent
fault event occurs when the voltage across the sense pins
exceeds V
FAULT
(after the blanking period of t
MIN
). This
begins the internal fault timer t
FAULT
. For the duration
of t
FAULT
, the LT4276 turns off PG and SG and pulls the
SFST pin to GND. After t
FAULT
expires, the LT4276 initi-
ates soft-start.
The fault and soft-start sequence repeats as long as the
short circuit or overload conditions persist. This condition
is recognized by the PG waveform shown in Figure 15
re
peating at an interval of t
FAULT
.
Figure 15: PG Waveform with Output Shorted
t
FAULT
4276 F14
LT4276
15
4276fa
For more information www.linear.com/LT4276
applicaTions inForMaTion
OVERTEMPERATURE PROTECTION
The IEEE 802.3 specification requires a PD to withstand
any applied voltage from 0V to 57V indefinitely. During
classification, however, the power dissipation in the LT4276
may be as high as 1.5W. The LT4276 can easily tolerate
this power for the maximum IEEE classification timing but
overheats if this condition persists abnormally.
The LT4276 includes an over-temperature protection
feature which is intended to protect the device during
momentary overload conditions. If the junction temperature
exceeds the over-temperature threshold, the LT4276 pulls
down HSGATE pin, disables classification, and disables
the switching regulator operation.
MAXIMUM DUTY CYCLE
The maximum duty cycle of the PG pin is modified by the
chosen t
PGDELAY
and f
SW
. It is calculated below:
MAX POWER SUPPLY DUTY CYCLE
= D
MAX
t
PGDELAY
f
SW
For an appropriate margin during transient operation, the
forward or flyback power supply should be designed so
that its maximum steady-state duty cycle should be about
10% lower than the LT4276 Maximum Power Supply Duty
Cycle calculated above.
EXTERNAL INTERFACE AND COMPONENT SELECTION
PoE Input Diode Bridge
PDs are required to polarity-correct its input voltage.
When diode bridges are used, the diode forward voltage
drops affect the voltage at the VPORT pin. The LT4276
is designed to tolerate these voltage drops. The voltage
parameters shown in the Electrical Characteristics are
specified at the LT4276 package pins.
For high efficiency applications, the LT4276 supports
an LT4321-based PoE ideal diode bridge that reduces
the forward voltage drop from 0.7V to nearly 20mV per
diode in normal operation, while maintaining IEEE 802.3
compliance.
Auxiliary Input Diode Bridge
Some PDs are required to receive AC or DC power from an
auxiliary power source. A diode bridge is typically required
to handle the voltage rectification and polarity correction.
In high efficiency applications, the voltage drop across the
rectifier cannot be tolerated. The LT4276 can be configured
with an LT4320-based ideal diode bridge to recover the
diode voltage drop and ease thermal design.
Input Capacitor
A 0.1µF capacitor is needed from VPORT to GND to meet
the input impedance requirement in IEEE 802.3 and to
properly bypass the LT4276. This capacitor must be placed
as close as possible to the VPORT and GND pins.
Transient Voltage Suppressor
The LT4276 specifies an absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events
due to Ethernet cable surges.
To protect the LT4276, install a unidirectional transient
voltage suppressor (TVS) such as an SMAJ58A between
the VPORT and GND pins. This TVS must be placed as close
as possible to the VPORT and GND pins of the LT4276.
For PD applications that require an auxiliary power input,
install a TVS between V
IN
and GND as close as possible
to the LT4276.
For extremely high cable discharge and surge protection
contact Linear Technology Applications.

LT4276BHUFD#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN PoE+ PD with Forward/Flyback Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union