Low Skew
Clock Buffer
CY7B9910
CY7B9920
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 1994 - Revised Jul
7
1997
Features
• All outputs skew <100 ps typical (250 max.)
• 15- to 80-MHz output operation
• Zero input to output delay
• 50% duty-cycle outputs
•
Outputs drive 50
Ω
terminated lines
• Low operating current
• 24-pin SOIC package
• Jitter: <200 ps peak to peak, <25 ps RMS
• Compatible with Pentium™-based processors
Functional Description
The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer
low-skew system clock distribution. These multiple-output
clock drivers optimize the timing of high-performance comput-
er systems. Eight individual drivers can each drive terminated
transmission lines with impedances as low as 50
Ω
while deliv-
ering minimal and specified output skews and full-swing logic
levels (CY7B9910 TTL or CY7B9920 CMOS).
The completely integrated PLL allows “zero delay” capability.
External divide capability, combined with the internal PLL, allows
distribution of a low-frequency clock that can be multiplied by virtu-
ally any factor at the clock destination. This facility minimizes clock
distribution difficulty while allowing maximum system clock speed
and flexibility.
Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept inputs from the reference frequency
(REF) input and the feedback (FB) input and generate correc-
tion information to control the frequency of the Voltage-Con-
trolled Oscillator (VCO). These blocks, along with the VCO,
form a Phase-Locked Loop (PLL) that tracks the incoming
REF signal.
VCO
The VCO accepts analog control inputs from the PLL filter
block and generates a frequency. The operational range of the
VCO is determined by the FS control pin.
Test Mode
The TEST input is a three-level input. In normal system oper-
ation, this pin is connected to ground, allowing the
CY7B9910/CY7B9920 to operate as explained above. (For
testing purposes, any of the three-level inputs can have a re-
movable jumper to ground, or be tied LOW through a 100
Ω
resistor. This will allow an external tester to change the state of
these pins.)
If the TEST input is forced to its MID or HIGH state, the device
will operate with its internal phase-locked loop disconnected,
and input levels supplied to REF will directly control all outputs.
Relative output to output functions are the same as in normal
mode.
Pentium is a trademark of Intel Corporation.
Logic Block Diagram Pin Configuration
7B9910–1
7B9910–2
TEST
FB
REF
Voltage
Controlled
Oscillator
FS
Q0
FILTER
PHASE
FREQ
DET
Q4
Q2
REF
V
CCQ
FS
NC
V
CCQ
V
CCN
Q0
Q1
GND
Q3
V
CCN
GND
TEST
NC
GND
V
CCN
Q7
Q6
GND
Q5
V
CCN
FB
SOIC
Top View
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
23
22
21
13
14
7B9910
7B9920
Q1
Q2
Q3
Q4
Q5
Q6
Q7
