CY7B9910
CY7B9920
5
t
OFALL
Output Fall Time
[17, 18]
0.15 1.0 1.5 0.5 2.0 3.0 ns
t
LOCK
PLL Lock Time
[19]
0.5 0.5 ms
t
JR
Cycle-to-Cycle Output Jitter Peak to Peak
[8]
200 200 ps
RMS
[8]
25 25 ps
Notes:
7. Test measurement levels for the CY7B9910 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B9920 are CMOS levels (V
CC
/2 to V
CC
/2). Test
conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9. For all three-state inputs, HIGH indicates a connection to V
CC
, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
holds an unconnected input to V
CC
/2.
10. The level to be set on FS is determined by the “normal” operating frequency (f
NOM
) of the VCO
(see Logic Block Diagram). The frequency appearing at the REF and
FB inputs will be f
NOM
when the output connected to FB is undivided. The frequency of the REF and FB inputs will be f
NOM
/X
when the device is configured for a frequency
multiplication by using external division in the feedback path of value X.
11. When the FS pin is selected HIGH, the REF input must not transition upon power-up until V
CC
has reached 4.3V.
12. Except as noted, all CY7B9920–2 and –5 timing parameters are specified to 80-MHz with a 30-pF load.
13. t
SKEW
is defined as the time between the earliest and the latest output transition among all outputs when all are loaded with 50 pF and terminated with 50
Ω
to
2.06V (CY7B9910) or V
CC
/2 (CY7B9920).
14. t
SKEW
is defined as the skew between outputs.
15. t
DEV
is the output-to-output skew between any two outputs on separate devices operating under the same conditions (V
CC
, ambient temperature, air flow, etc.).
16. t
ODCV
is the deviation of the output from a 50% duty cycle.
17. Specified with outputs loaded with 30 pF for the CY7B99X0–2 and –5 devices and 50 pF for the CY7B99X0–7 devices. Devices are terminated through 50
Ω
to 2.06V (CY7B9910) or V
CC
/2 (CY7B9920).
18. t
ORISE
and t
OFALL
measured between 0.8V and 2.0V for the CY7B9910 or 0.8V
CC
and 0.2V
CC
for the CY7B9920.
19. t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until t
PD
is within specified limits.
CY7B9910–5 CY7B9920–5
Parameter Description Min. Typ. Max. Min. Typ. Max. Unit
Switching Characteristics
Over the Operating Range
[7]
(continued)
CY7B9910–7 CY7B9920–7
Parameter Description Min. Typ. Max. Min. Typ. Max. Unit
f
NOM
Operating Clock
Frequency in MHz
FS = LOW
[9, 10]
15 30 15 30 MHz
FS = MID
[9, 10]
25 50 25 50
FS = HIGH
[9, 10, 11]
40 80 40 80
[12]
t
RPWH
REF Pulse Width HIGH 5.0 5.0 ns
t
RPWL
REF Pulse Width LOW 5.0 5.0 ns
t
SKEW
Zero Output Skew (All Outputs)
[13, 14]
0.3 0.75 0.3 0.75 ns
t
DEV
Device-to-Device Skew
[8, 15]
1.5 1.5 ns
t
PD
Propagation Delay, REF Rise to FB Rise –0.7 0.0 +0.7 –0.7 0.0 +0.7 ns
t
ODCV
Output Duty Cycle Variation
[16]
–1.2 0.0 +1.2 –1.2 0.0 +1.2 ns
t
ORISE
Output Rise Time
[17, 18]
0.15 1.5 2.5 0.5 3.0 5.0 ns
t
OFALL
Output Fall Time
[17, 18]
0.15 1.5 2.5 0.5 3.0 5.0 ns
t
LOCK
PLL Lock Time
[19]
0.5 0.5 ms
t
JR
Cycle-to-Cycle Output
Jitter
Peak to Peak
[8]
200 200 ps
t
JR
RMS
[8]
25 25 ps
