CY7B9910
CY7B9920
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
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Operational Mode Descriptions
Figure 1
shows the device configured as a zero-skew clock
buffer. In this mode the 7B9910/9920 can be used as the basis
for a low-skew clock distribution tree. The outputs are aligned
and may each drive a terminated transmission line to an inde-
pendent load. The FB input can be tied to any output and the
operating frequency range is selected with the FS pin. The
low-skew specification, coupled with the ability to drive termi-
nated transmission lines (with impedances as low as 50
ohms), allows efficient printed circuit board design.
Figure 2
shows the CY7B9910/9920 connected in series to
construct a zero-skew clock distribution tree between boards.
Cascaded clock buffers will accumulate low-frequency jitter
because of the non-ideal filtering characteristics of the PLL
filter. It is not recommended that more than two clock buffers
be connected in series.
Figure 1. Zero-Skew and/or Zero-Delay Clock Driver
SYSTEM
CLOCK
7B9910–9
FB
REF
FS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
TEST
Z
0
LOAD
LOAD
LOAD
LOAD
REF
Z
0
Z
0
Z
0
Figure 2. Board-to-Board Clock Distribution
SYSTEM
CLOCK
Z
0
7B9910–10
FB
REF
FS
TEST
REF
REF
FS
FB
LOAD
LOAD
LOAD
LOAD
LOAD
TEST
Z
0
Z
0
Z
0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
