2010 Sep 16 4
NXP Semiconductors Product specification
N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR
STATIC CHARACTERISTICS
T
j
=25C unless otherwise specified.
Note
1. R
G1
connects G
1
to V
GG
=5V.
DYNAMIC CHARACTERISTICS
Common source; T
amb
=25C; V
G2-S
=4V; V
DS
=5V; I
D
= 12 mA; unless otherwise specified.
Note
1. Measured in Fig.21 test circuit.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
(BR)DSS
drain-source breakdown voltage V
G1-S
=V
G2-S
=0; I
D
=10A10 V
V
(BR)G1-SS
gate 1-source breakdown voltage V
G2-S
=V
DS
=0; I
G1-S
=10mA 6 V
V
(BR)G2-SS
gate 2-source breakdown voltage V
G1-S
=V
DS
=0; I
G2-S
=10mA 6 V
V
(F)S-G1
forward source-gate 1 voltage V
G2-S
=V
DS
=0; I
S-G1
=10mA 0.5 1.5 V
V
(F)S-G2
forward source-gate 2 voltage V
G1-S
=V
DS
=0; I
S-G2
=10mA 0.5 1.5 V
V
G1-S(th)
gate 1-source threshold voltage V
G2-S
=4V; V
DS
=5V; I
D
=100A0.31.0V
V
G2-S(th)
gate 2-source threshold voltage V
G1-S
=5V; V
DS
=5V; I
D
=100A0.31.2V
I
DSX
drain-source current V
G2-S
=4V; V
DS
=5V; R
G1
=120k;
note 1
816mA
I
G1-SS
gate 1 cut-off current V
G2-S
=V
DS
=0; V
G1-S
=5V 50 nA
I
G2-SS
gate 2 cut-off current V
G1-S
=V
DS
=0; V
G2-S
=4V 20 nA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
y
fs
forward transfer admittance pulsed; T
j
=25C 253040mS
C
ig1-ss
input capacitance at gate 1 f = 1 MHz 1.7 2.2 pF
C
ig2-ss
input capacitance at gate 2 f = 1 MHz 1 pF
C
oss
output capacitance f = 1 MHz 0.85 pF
C
rss
reverse transfer capacitance f = 1 MHz 15 30 fF
F noise figure f = 10.7 MHz; G
S
=20mS; B
S
=0 911dB
f=400MHz; Y
S
=Y
Sopt
0.9 1.5 dB
f=800MHz; Y
S
=Y
Sopt
1.1 1.8 dB
G
tr
power gain f = 200 MHz; G
S
=2mS; B
S
=B
Sopt
;
G
L
= 0.5 mS; B
L
=B
Lopt
34.5 dB
f=400MHz; G
S
=2mS; B
S
=B
Sopt
;
G
L
=1mS; B
L
=B
Lopt
30.5 dB
f=800MHz; G
S
= 3.3 mS; B
S
=B
Sopt
;
G
L
=1mS; B
L
=B
Lopt
26.5 dB
X
mod
cross-modulation input level for k = 1%; f
w
=50MHz;
f
unw
=60MHz; note1
at 0 dB AGC 90 dBV
at 10 dB AGC 92 dBV
at 40 dB AGC 100 105 dBV