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954101DFLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Integrated
Circuit
Systems, Inc.
ICS954101
0815G—12/02/08
Pin Configuration
Recommended Application:
CK410 clock, Intel Yellow Cover part
Output Features:
• 2 - 0.7V current-mode differential CPU pairs
• 6 - 0.7V current-mode differential SRC pair for SATA and
PCI-E
• 1 - 0.7V current-mode differential CPU/SRC selectable
pair
• 6 - PCI (33MHz)
• 3 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 1 - DOT, 96MHz, 0.7V current differential pair
• 1 - REF, 14.318MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter <125ps
• PCI outputs cycle-cycle jitter < 500ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
Programmable Timing Control Hub™ for Desktop P4™ Systems
Functionality
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA and
PCI-Express
• Supports spread spectrum modulation, 0 to -0.5%
down spread
• Supports CPU clks up to 400MHz
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• Supports undriven differential CPU, SRC pair in PD#
for power management.
56-pin SSOP & TSSOP
VDDPCI 1 56 PCICLK2
GND 2 55 PCICLK1
PCICLK3 3 54 PCICLK0
PCICLK4 4 53 FS_C/TEST_SEL
PCICLK5 5 52 REFOUT
GND 6 51 GND
VDDPCI 7 50 X1
ITP_EN/PCICLK_F0 8 49 X2
PCICLK_F1 9 48 VDDREF
PCICLK_F210 47SDATA
VDD4811 46SCLK
USB_48MHz 12 45 GND
GND 13 44 CPUCLKT0
DOTT_96MHz 14 43 CPUCLKC0
DOTC_96MHz 15 42 VDDCPU
FS_B/TEST_MODE 16 41 CPUCLKT1
Vtt_PwrGd#/PD 17 40 CPUCLKC1
FS_A_410 18 39 IREF
SRCCLKT1 19 38 GNDA
SRCCLKC1 20 37 VDDA
VDDSRC 21 36 CPUCLKT2_ITP/SRCCLKT_7
SRCCLKT2 22 35 CPUCLKC2_ITP/SRCCLKC_7
SRCCLKC2 23 34 VDDSRC
SRCCLKT3 24 33 SRCCLKT6
SRCCLKC3 25 32 SRCCLKC6
SRCCLKT4_SATA 26 31 SRCCLKT5
SRCCLKC4_SATA 27 30 SRCCLKC5
VDDSRC 28 29 GND
ICS954101
FS_C
1
FS_B
2
FS_A
2
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
0
0 0 266.66 100.00 33.33 14.318 48.00 96.00
0
0 1 133.33 100.00 33.33 14.318 48.00 96.00
0
1 0 200.00 100.00 33.33 14.318 48.00 96.00
0
1 1 166.66 100.00 33.33 14.318 48.00 96.00
1
0 0 333.33 100.00 33.33 14.318 48.00 96.00
1
0 1 100.00 100.00 33.33 14.318 48.00 96.00
1
1 0 400.00 100.00 33.33 14.318 48.00 96.00
1
1 1 14.318 48.00 96.00
1.
FS_C is a three-level input. Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Suppl
y
/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_B and FS_A are low-threshold inputs. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Suppl
y
/Common Output Parameters Table for correct values.
RESERVED
2
Integrated
Circuit
Systems, Inc.
ICS954101
0815G—12/02/08
Pin Description
Pin # PIN NAME PIN TYPE DESCRIPTION
1 VDDPCI PWR Power su
pp
l
y
for PCI clocks, nominal 3.3V
2 GND PWR Ground
p
in.
3 PCICLK3 OUT PCI clock out
p
ut.
4 PCICLK4 OUT PCI clock out
p
ut.
5 PCICLK5 OUT PCI clock out
p
ut.
6 GND PWR Ground
p
in.
7 VDDPCI PWR Power su
pp
l
y
for PCI clocks, nominal 3.3V
8 ITP_EN/PCICLK_F0 I/O
Free runnin
g
PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC
p
air
9 PCICLK_F1 OUT Free runnin
g
PCI clock not affected b
y
PCI_STOP# .
10 PCICLK_F2 OUT Free runnin
g
PCI clock not affected b
y
PCI_STOP# .
11 VDD48 PWR Power
in for the 48MHz out
ut.3.3V
12 USB_48MHz OUT 48.00MHz USB clock
13 GND PWR Ground
p
in.
14 DOTT_96MHz OUT True clock of differential
p
air for 96.00MHz DOT clock.
15 DOTC_96MHz OUT Com
p
lement clock of differential
p
air for 96.00MHz DOT clock.
16 FS_B/TEST_MODE IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
17 Vtt_PwrGd#/PD IN
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin
used to put the device into a low power state. The internal clocks, PLLs
and the cr
y
stal oscillator are sto
pp
ed.
18 FS_A_410 IN
3.3V tolerant low threshold input for CPU frequency selection. This pin
requires CK410 FSA. Refer to input electrical characteristics for Vil_FS
and Vih_FS threshold values.
19 SRCCLKT1 OUT True clock of differential SRC clock
p
air.
20 SRCCLKC1 OUT Com
p
lement clock of differential SRC clock
p
air.
21 VDDSRC PWR Su
pp
l
y
for SRC clocks, 3.3V nominal
22 SRCCLKT2 OUT True clock of differential SRC clock
p
air.
23 SRCCLKC2 OUT Com
p
lement clock of differential SRC clock
p
air.
24 SRCCLKT3 OUT True clock of differential SRC clock
p
air.
25 SRCCLKC3 OUT Com
p
lement clock of differential SRC clock
p
air.
26 SRCCLKT4_SATA OUT True clock of differential SRC/SATA
p
air.
27 SRCCLKC4_SATA OUT Com
p
lement clock of differential SRC/SATA
p
air.
28 VDDSRC PWR Supply for SRC clocks, 3.3V nominal
3
Integrated
Circuit
Systems, Inc.
ICS954101
0815G—12/02/08
Pin Description (Continued)
Pin # PIN NAME TYPE DESCRIPTION
29 GND PWR Ground
p
in.
30 SRCCLKC5 OUT Com
p
lement clock of differential SRC clock
p
air.
31 SRCCLKT5 OUT True clock of differential SRC clock
p
air.
32 SRCCLKC6 OUT Com
p
lement clock of differential SRC clock
p
air.
33 SRCCLKT6 OUT True clock of differential SRC clock
p
air.
34 VDDSRC PWR Su
pp
l
y
for SRC clocks, 3.3V nominal
35 CPUCLKC2_ITP/SRCCLKC_7 OUT
Complimentary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC
output. These are current mode outputs. External resistors are required
for volta
g
e bias. Selected b
y
ITP_EN in
p
ut.
36 CPUCLKT2_ITP/SRCCLKT_7 OUT
True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These
are current mode outputs. External resistors are required for voltage bias.
Selected b
y
ITP_EN in
p
ut.
37 VDDA PWR 3.3V
p
ower for the PLL core.
38 GNDA PWR Ground
p
in for the PLL core.
39 IREF OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
40 CPUCLKC1 OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
41 CPUCLKT1 OUT
True clock of differential pair CPU outputs. These are current mode
out
p
uts. External resistors are re
q
uired for volta
g
e bias.
42 VDDCPU PWR Su
pp
l
y
for CPU clocks, 3.3V nominal
43 CPUCLKC0 OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
44 CPUCLKT0 OUT
True clock of differential pair CPU outputs. These are current mode
out
p
uts. External resistors are re
q
uired for volta
g
e bias.
45 GND PWR Ground
p
in.
46 SCLK IN Clock
p
in of SMBus circuitr
y
, 5V tolerant.
47 SDATA I/O Data
p
in for SMBus circuitr
y
, 5V tolerant.
48 VDDREF PWR Ref, XTAL
p
ower su
pp
l
y
, nominal 3.3V
49 X2 OUT Cr
y
stal out
p
ut, Nominall
y
14.318MHz
50 X1 IN Cr
y
stal in
p
ut, Nominall
y
14.318MHz.
51 GND PWR Ground
p
in.
52 REFOUT OUT Reference Clock out
p
ut
53 FS_C/TEST_SEL IN
3.3V tolerant input for CPU frequency selection. Low voltage threshold
inputs, see input electrical characteristics for Vil_FS and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
54 PCICLK0 OUT PCI clock out
p
ut.
55 PCICLK1 OUT PCI clock out
p
ut.
56 PCICLK2 OUT PCI clock output.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

954101DFLFT

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Description:
IC CTRL HUB PROGR TIMING 56-SSOP
Lifecycle:
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