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954101DFLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
4
Integrated
Circuit
Systems, Inc.
ICS954101
0815G—12/02/08
ICS954101 follows Intel CK410 Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets. ICS954101 is driven with a 14.318MHz crystal. It generates CPU outputs up
to 400MHz. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support.
General Description
Block Diagram
Power Groups
VDD GND
48 51 Xtal, Ref
1,7 2,6 PCICLK outputs
21,28,34 29 SRCCLK outputs
37 38 Master clock, CPU Analog
11 13 DOT, USB, PLL_48
42 45 CPUCLK clocks
Description
Pin Number
I REF
PLL2
Frequency
Dividers
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
48MHz, USB
X1
X2
XTAL
SDATA
SCLK
V
tt_PWRGD#/PD
FS_A
FS_B
FS_C
ITP_EN
TEST_MODE
TEST_SEL
Control
Logic
REFOUT
CPUCLKT (2:0)
CPUCLKC (2:0)
SRCCLKT (7:1)
SRCCLKC (7:1)
PCICLK (5:0)
PCICLKF (2:0)
96MHz_DOTT_0
96MHz_DOTC_0
5
Integrated
Circuit
Systems, Inc.
ICS954101
0815G—12/02/08
General I
2
C serial interface information for the ICS954101
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byte
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
6
Integrated
Circuit
Systems, Inc.
ICS954101
0815G—12/02/08
Absolute Max
Symbol Parameter Min Max Units
VDD_A 3.3V Core Supply Voltage V
DD
+ 0.5V V
VDD_In 3.3V Logic Input Supply Voltage GND - 0.5 V
DD
+ 0.5V V
Ts Storage Temperature -65 150
°
C
Tambient Ambient Operating Temp 0 70 °C
Tcase Case Temperature 115 °C
ESD prot
Input E
S
D protection
human body model
2000 V
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage V
IH
3.3 V +/-5% 2 V
DD
+ 0.3 V
Input Low Voltage V
IL
3.3 V +/-5% V
SS
- 0.3 0.8 V
Input High Current I
IH
V
IN
= V
D
D
-5 5 uA
I
IL1
V
IN
= 0 V; Inputs with no pull-
up resistors
-5 uA
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200 uA
Low Threshold Input High
Voltage
V
IH_FS
3.3 V +/-5% 0.7 V
DD
+ 0.3 V
Low Threshold Input Low
Volta
g
e
V
IL_FS
3.3 V +/-5% V
SS
- 0.3 0.35 V
Operating Supply Current I
DD3. 3OP
3.3 V +/-5%, Full Load 350 500 mA
all diff pairs driven 70 mA
all differential pairs tri-stated 12 mA
Input Frequency
3
F
i
V
DD
= 3.3 V 14.31818 MHz 3
Pin Inductance
1
L
p
in
7nH1
C
IN
Logic Inputs 5 pF 1
C
OUT
Output pin capacitance 6 pF 1
C
INX
X1 & X2 pins 5 pF 1
Clk Stabilization
1,2
T
STAB
From V
DD
Power-Up or de-
assertion of PD# to 1st clock
1.8 ms 1,2
Modulation Frequency Trian
g
ular Modulation 30 33 kHz 1
Tdrive_PD#
CPU output enable after
PD# de-assertion
300 us 1
Tfall_Pd# PD# fall time of 5 ns 1
Trise_Pd# PD# rise time of 5 ns 2
SMBus Voltage V
D
D
2.7 5.5 V 1
Low-level Output Voltage V
OLSMBUS
@ I
PULLUP
0.4 V 1
C
urrent sinking at V
OL
= 0.4
V
I
PULLUP
4mA1
SCLK/SDATA
Clock/Data Rise Time
T
RI2C
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA
Clock/Data Fall Time
T
FI 2C
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
See timin
g
dia
g
rams for timin
g
requirements.
3
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm accuracy on PLL outputs.
Input Low Current
Powerdown Current I
DD3.3PD
Input Capacitance
1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

954101DFLFT

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Buy 954101DFLFT
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Description:
IC CTRL HUB PROGR TIMING 56-SSOP
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