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954101DFLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
10
Integrated
Circuit
Systems, Inc.
ICS954101
0815G—12/02/08
Electrical Characteristics - DOT, 96MHz 0.7V Current Mode Differential Pair
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2
Ω
, R
P
=49.9
Ω, Ι
REF
= 475Ω
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Current Source
Out
p
ut Im
p
edance
Zo
V
O
= V
x
3000
Ω
1
Volta
g
e Hi
g
hVHi
g
h 660 850 1
Volta
g
e Low VLow -150 150 1
Max Volta
g
e Vovs 1150 1
Min Volta
g
e Vuds -300 1
Crossing Voltage
(
abs
)
Vcross(abs) 250 550 mV 1
Crossing Voltage
(
var
)
d-Vcross
Variation of crossing over
all ed
g
es
140 mV 1
Long Accuracy ppm
see Tperiod min-max
values
-100 100 ppm 1,2
Avera
g
e period Tperiod
96.00MHz nominal 10.4135 10.4198 ns 2
Absolute min period Tabsmin 96.00MHz nominal 10.1635 ns 1,2
Rise Time
t
r
V
OL
= 0.175V, V
OH
=
0.525V
175 700 ps 1
Fall Time
t
f
V
OH
= 0.525V V
OL
=
0.175V
175 700 ps 1
Rise Time Variation
d-t
r
125 ps 1
Fall Time Variation
d-t
f
125 ps 1
Duty Cycle
d
t3
Measurement from
differential wavefrom
45 55 % 1
Jitter, Cycle to cycle
t
jcyc-cyc
Measurement from
differential wavefrom
250 ps 1
1
Guaranteed b
y
desi
g
n, not 100% tested in
p
roduction.
2
All Lon
g
Term Accurac
y
and Clock Period s
p
ecifications are
g
uaranteed assumin
g
that REFout
p
ut is at 14.31818MHz
Measurement on single
ended signal using
mV
Statistical measurement
on single ended signal
mV
11
Integrated
Circuit
Systems, Inc.
ICS954101
0815G—12/02/08
Electrical Characteristics - REF-14.318MHz
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
= 20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Lon
g
Accurac
y
ppm see Tperiod min-max values -300 300 ppm 1
Clock period T
p
eriod
14.318MHz output nominal 69.82700 69.85500 ns 1
Absolute Min/Max Clock
period
T
abs
Nominal 68.82033 70.86224 ns 2
Output High Voltage V
OH
I
OH
= -1 mA 2.4 V 1
Output Low Voltage V
OL
I
OL
= 1 mA 0.4 V 1
Output High Current I
OH
V
OH
@MIN = 1.0 V,
V
OH
@MAX = 3.135 V
-29 -23 mA 1
Output Low Current I
OL
V
OL
@MIN = 1.95 V,
V
OL
@MAX = 0.4 V
29 27 mA 1
Rise Time t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V 1 2 ns 1
Fall Time t
f1
V
OH
= 2.4 V, V
OL
= 0.4 V 1 2 ns 1
Duty Cycle d
t1
V
T
= 1.5 V 45 55 % 1
Jitter t
jcyc-cyc
V
T
= 1.5 V 1000 ps 1
1
Guaranteed b
y
desi
g
n, not 100% tested in production.
12
Integrated
Circuit
Systems, Inc.
ICS954101
0815G—12/02/08
I
2
C Table: Read-Back Register
Pin # Nam
e
Control Function T
yp
e0 1 PWD
Bit 7
CPUCLK2/RCCLK7 Enable Output Enable RW DISABLE ENABLE 1
Bit 6
SRCCLK6 Enable Output Enable RW DISABLE ENABLE 1
Bit 5
SRCCLK5 Enable Output Enable RW DISABLE ENABLE 1
Bit 4
SRCCLK4 Enable Output Enable RW DISABLE ENABLE 1
Bit 3
SRCCLK3 Enable Output Enable RW DISABLE ENABLE 1
Bit 2
SRCCLK2 Enable Output Enable RW DISABLE ENABLE 1
Bit 1
SRCCLK1 Enable Output Enable RW DISABLE ENABLE 1
Bit 0
I
2
C Table: Spreading and Device Behavior Control Register
Pin # Nam
e
Control Function T
yp
e0 1 PWD
Bit 7
PCI_F0 Enable Output Enable RW Disable Enable 1
Bit 6
DOT_96MHz Output Enable RW Disable Enable 1
Bit 5
USB_48MHz Enable Output Enable RW Disable Enable 1
Bit 4
REFOUT Enable Output Enable RW Disable Enable 1
Bit 3
1
Bit 2
CPUT1/CPUC1 Output Enable RW Disable Enable 1
Bit 1
CPUT0/CPUC0 Output Enable RW Disable Enable 1
Bit 0
Spread Spectrum Mode Spread Off RW SPREAD OFF
SPREAD
ON
0
I
2
C Table: Output Control Register
Pin # Nam
e
Control Function T
yp
e0 1 PWD
Bit 7
PCICLK5 Output Enable RW Disable Enable 1
Bit 6
PCICLK4 Output Enable RW Disable Enable 1
Bit 5
PCICLK3 Out
p
ut Enable RW Disable Enable 1
Bit 4
PCICLK2 Out
p
ut Enable RW Disable Enable 1
Bit 3
PCICLK1 Out
p
ut Enable RW Disable Enable 1
Bit 2
PCICLK0 Output Enable RW Disable Enable 1
Bit 1
PCI_F2 Enable Output Enable RW Disable Enable 1
Bit 0
PCI_F1 Enable Output Enable RW Disable Enable 1
I
2
C Table: Output Control Register
Pin # Nam
e
Control Function T
yp
e0 1 PWD
Bit 7
CPU_ITP/SRCCLK7 RW Free-Running Stoppable 0
Bit 6
SRCCLK6 RW Free-Runnin
g
Stoppable 0
Bit 5
SRCCLK5 RW Free-Running Stoppable 0
Bit 4
SRCCLK4 RW Free-Runnin
g
Stoppable 0
Bit 3
SRCCLK3 RW Free-Running Stoppable 0
Bit 2
SRCCLK2 RW Free-Runnin
g
Stoppable 0
Bit 1
SRCCLK1 RW Free-Running Stoppable 0
Bit 0
0
54
4
3
56
55
30,31
26,27
32,33
9
B
y
te 0
35,36
32,33
30,31
26,27
24,25
22,23
19,20
B
y
te 2
5
10
24,25
22,23
19,20
-
43,44
-
40,41
12
52
B
y
te 3
Free-Running
Control
default:
not affected by
PCI/SRC_STOP
(Byte 6, bit 3)
RESERVED
RESERVED-
B
y
te 1
54
14,15
RESERVED
35,35
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

954101DFLFT

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Buy 954101DFLFT
Manufacturer:
Description:
IC CTRL HUB PROGR TIMING 56-SSOP
Lifecycle:
New from this manufacturer.
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