NCP3102C
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9
DETAILED OPERATING DESCRIPTION
General
NCP3102C is a high efficiency integrated wide input
voltage 10 A synchronous PWM buck converter designed to
operate from a 4.5 V to 13.2 V supply. The output voltage
of the converter can be precisely regulated down to 800 mV
+
1.0% when the VFB pin is tied to the output voltage. The
switching frequency is internally set to 275 kHz. A high gain
Operational Transconductance Error Amplifier (OTEA) is
used for feedback and stabilizing the loop.
Input Voltage
The NCP3102C can be used in many applications by
using the V
CC
and PWRVCC pins together or separately.
The PWRVCC pin provides voltage to the switching
MOSFETS. The V
CC
pin provides voltage to the control
circuitry and driver stage.
If the V
CC
and the PWRVCC pin are not tied together, the
input voltage of the PWRVCC pin can accept 2.7 V to 18 V.
If the V
CC
and PWRVCC pins are tied together the input
voltage range is 4.5 V to 13.2 V.
Duty Cycle and Maximum Pulse Width Limits
In steady state DC operation, the duty cycle will stabilize
at an operating point defined by the ratio of the input to the
output voltage. The NCP3102C can achieve an 82% duty
ratio. The part has a built in off--time which ensures that the
bootstrap supply is charged every cycle. The NCP3102C is
capable of a 100 ns pulse width (minimum) and allows a
12 V to 0.8 V conversion at 275 kHz. The duty cycle limit
and the corresponding output voltage are shown below in
graphical format in Figure 17. The green area represents the
safe operating area for the lowest maximum operational
duty cycle for 4.5 V and 13.2 V.
Figure 17. Maximum Input to Output Voltage
4. 5
5. 5
6. 5
7. 5
8. 5
9. 5
10. 5
11. 5
12. 5
3. 5 4. 5 5. 5 6.5 7. 5 8. 5 9. 5 10. 5 11. 5
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
D
max
=0.88
D
max
=0.82
Input voltage range (VCC and BST)
The input voltage range for both VCC and BST is 4.5 V
to 13.2 V with reference to GND and PHS, respectively.
Although BST is rated at 13.2 V with reference to PHS, it
can also tolerate 26.5 V with respect to GND.
External Enable/Disable
Once the input voltage has exceeded the boost and UVLO
thresholdat3.82VandV
CC
threshold at 4 V, the COMP pin
starts to rise. The PWRPHS node is tri--stated until the
COMP voltage exceeds 830 mV. Once the 830 mV
threshold is exceeded, the part starts to switch and is
considered enabled. When the COMP pin voltage is pulled
below the 400 mV threshold, it disables the PWM logic, the
top MOSFET is driven off, and the bottom MOSFET is
driven on as shown in Figure 18. In the disabled mode, the
OTA output source current is reduced to 10 mA.
When disabling the NCP3102Cusing the COMP / Disable
pin, an open collector or open drain drive should be used as
shown in Figure 19.
COMP
0.83 V
BG
TG
Figure 18. Enable/Disable Driver State Diagram
2N7002E
COMP
Disable
Gate Signal Enable
COMP
Enable
Disable
Base Signal
MMBT3904
Figure 19. Recommended Disable Circuits
Power Sequencing
Power sequencing can be achieved with NCP3102C using
two general purpose bipolar junction transistors or
MOSFETs. An example of the power sequencing circuit
using the external components is shown in Figure 20.
NCP3102C
FB1
1.0V
VSW
COMP
VIN
NCP3102C
FB1
3.3V
VSW
COMP
Figure 20. Power Sequencing
