ADC1207S080HW/C1:5 Datasheet ADC1207S080HW/C1:1, ADC1207S080HW/C1:5 | P10-P12

Product data sheet Rev. 02 — 7 August 2008 10 of 21

NXP Semiconductors

ADC1207S080

Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling

10. Additional information relating to Table 5

[1] X = don’t care.

Table 6. Output coding with differential inputs

i(IN)

−

i(INN)

= 1.9 V; V

ref(fs)

CCA1

−

1.87 V; typical values to AGND.

Code V

i(IN)

(V) V

i(INN)

(V) IR Binary outputs

(D11 to D0)

Two’s complement outputs

(D11 to D0)

Underﬂow < 2.675 > 3.625 0 0000 0000 0000 1000 0000 0000

0 2.675 3.625 1 0000 0000 0000 1000 0000 0000

1 - - 1 0000 0000 0001 1000 0000 0001

↓ ↓↓↓↓ ↓

2047 3.15 3.15 1 0111 1111 1111 1111 1111 1111

↓ ↓↓↓↓ ↓

4094 - - 1 1111 1111 1110 0111 1111 1110

4095 3.625 2.675 1 1111 1111 1111 0111 1111 1111

Overﬂow > 3.625 < 2.675 0 1111 1111 1111 0111 1111 1111

Table 7. Mode selection

Two’s complement output (OTC) Chip enable input (CE_N) Data output (D0 to D11; IR)

0 0 binary; active

1 0 two’s complement; active

[1]

1 high-impedance

Fig 3. Output timing diagram

CLK

0.5 V

D0 to D11

CCO

− 0.5 V

50 %

data

n − 1

data

n + 1

d(o)

d(s)

h(o)

014aaa432

sample

n + 1

sample

n + 2

sample

n + 3

sample

n + 4

Product data sheet Rev. 02 — 7 August 2008 11 of 21

NXP Semiconductors

ADC1207S080

Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling

The ADC1207S080 allows modifying the ADC full-scale. This could be done with FSIN

(full-scale input) according to Figure 5.

(1) f

1H = 15 MHz; 0 dBc

(2) f

2H = 5.1 MHz; −79.6 dBc

(3) f

3H = 9.88 MHz; −82.1 dBc

(4) f

4H = 20.1 MHz; −80.6 dBc

(5) f

5H = 30 MHz; −74.7 dBc

(6) f

6H = 35.1 MHz; −93.9 dBc

THD (5H): −72.2 dBc

SFDR: 74.7 dBc

Fig 4. Single tone; f

= 175 MHz; f

CLK

=80MHz

Fig 5. ADC full-scale; V

i(a)(p-p)

as a function of V

ref(fs)

(MHz)

0 40302010

014aaa435

−80

−120

−40

power

spectrum

(dBc)

−160

(1)

(5) (6)(4)(3)(2)

ref(fs)

(V)

1.4 2.22.01.81.6

014aaa436

1.8

1.6

2.0

2.2

i(a)(p-p)

(V)

1.4

Product data sheet Rev. 02 — 7 August 2008 12 of 21

NXP Semiconductors

ADC1207S080

Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling

The ADC1207S080 generates an adjustable clock output called Complete Conversion

Signal (CCS), which can be used to control the acquisition of converted output data by the

digital circuit connected to the ADC1207S080 output data bus. Two logic inputs, DEL0 and

DEL1 pins, allow adjusting the delay of the edge of the CCS signal to achieve an optimal

position in the stable, usable zone of the data.

Table 8. Complete conversion signal selection

DEL1 DEL0 CCS output

0 0 high-impedance

0 1 active, typical delay 0.3 ns

1 0 active, typical delay 1.3 ns

1 1 active, typical delay 2.3 ns

(1) t

d(CSS)

is referenced to the middle of the active data.

Fig 6. Complete conversion signal timing diagram

014aaa433

D0 to D11

(1)

CCS

d(CCS)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

ADC1207S080HW/C1:5

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ADC1207S080HW/C1:5

ADC1207S080HW/C1:5

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