ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 9 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
[1] The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
a) PECL mode 1: (DC levels vary 1:1 with V
CCD
) CLK and CLKN inputs are at differential PECL levels.
b) PECL mode 2: (DC levels vary 1:1 with V
CCD
) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor.
c) PECL mode 3: (DC levels vary 1:1 with V
CCD
) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level
of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling
takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF
capacitor.
e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has
to be connected to the ground.
[2] Guaranteed by design.
[3] The ADC input range can be adjusted with an external reference connected to pin FSIN. This voltage has to be referenced to V
CCA.
[4] Output data acquisition: the output data is available after the maximum delay of t
d(o)
.
[5] The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
[6] The total harmonic distortion is obtained with the addition of the first five harmonics.
[7] The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency.
[8] Intermodulation measured relative to either tone with analog input frequencies f
i
1 and f
i
2. The two input signals have the same
amplitude and the total amplitude of both signals provides full-scale to the converter (−6 dB below full-scale for each input signal). IMD3
is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product; IMD2 is the ratio
of the RMS value of either input tone to the RMS value of the worst case second order intermodulation product.
S/N signal-to-noise ratio f
i
= 21.4 MHz
[7]
- 67.4 - dBc
f
i
= 93 MHz 63 67.2 - dBc
f
i
= 175 MHz - 66.5 - dBc
SFDR spurious free dynamic
range
f
i
= 21.4 MHz - 76 - dBc
f
i
= 93 MHz 68 78 - dBc
f
i
= 175 MHz - 74 - dBc
ACPR adjacent channel power
ratio
f
i
= 93 MHz; 5 MHz
channel spacing;
B = 3.84 MHz
-70- dB
IMD2 second-order
intermodulation
distortion
f
i
1 = 21 MHz;
f
i
2=22MHz
[8]
- −89 - dBFS
f
i
1 = 91.5 MHz;
f
i
2 = 94.5 MHz
- −86 - dBFS
f
i
1 = 174 MHz;
f
i
2 = 176 MHz
- −83 - dBFS
IMD3 third-order
intermodulation
distortion
f
i
1 = 21 MHz;
f
i
2=22MHz
[8]
- −88 - dBFS
f
i
1 = 91.5 MHz;
f
i
2 = 93.5 MHz
- −82 - dBFS
f
i
1 = 174 MHz;
f
i
2 = 176 MHz
- −83 - dBFS
Table 5. Characteristics
…continued
V
CCA
= 4.75 V to 5.25 V; V
CCD
= 4.75 V to 5.25 V; V
CCO
= 2.7 V to 3.6 V; AGND and DGND shorted together; T
amb
=
−
40
°
C
to +85
°
C; V
i(IN)
−
V
i(INN)
=
−
0.5 dBFS; V
ref(fs)
=V
CCA
−
1.87 V; V
I(cm)
=V
CCA
−
1.95 V; typical values measured at
V
CCA
=V
CCD
=5V, V
CCO
= 3.3 V, T
amb
=25
°
C and C
L
= 10 pF; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
