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ADC1207S080HW/C1:5

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 4 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
[1] P: power supply; G: ground; I: input; O: output.
DGND2 17 G digital ground 2
CE_N 18 I chip enable input (CMOS level; active LOW)
OTC 19 I control input for two’s complement output (active HIGH)
OGND 20 G data output ground
V
CCO
21 P data output supply voltage (3.3 V)
OGND 22 G data output ground
V
CCO
23 P data output supply voltage (3.3 V)
IR 24 O in-range output
D11 25 O data output bit 11 (Most Significant Bit (MSB))
D10 26 O data output bit 10
D9 27 O data output bit 9
D8 28 O data output bit 8
D7 29 O data output bit 7
D6 30 O data output bit 6
D5 31 O data output bit 5
D4 32 O data output bit 4
D3 33 O data output bit 3
D2 34 O data output bit 2
D1 35 O data output bit 1
D0 36 O data output bit 0 (Least Significant Bit (LSB))
CCS 37 O complete conversion signal output
DGND1 38 G digital ground 1
CLKN 39 I complementary clock input
CLK 40 I clock input
V
CCD1
41 P digital supply voltage 1 (5.0 V)
DGND1 42 G digital ground 1
AGND2 43 G analog ground 2
V
CCA2
44 P analog supply voltage 2 (5.0 V)
V
CCA1
45 P analog supply voltage 1 (5.0 V)
AGND1 46 G analog ground 1
V
CCA1
47 P analog supply voltage 1 (5.0 V)
AGND1 48 G analog ground 1
DGND exposed
die pad
G digital ground
Table 2. Pin description
…continued
Symbol Pin Type
[1]
Description
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 5 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
7. Limiting values
[1] The supply voltages V
CCA
and V
CCD
may have any value between −0.5 V and +7.0 V provided that the
supply voltage differences ∆V
CC
are respected.
[2] The supply voltage V
CCO
may have any value between −0.5 V and +5.0 V provided that the supply voltage
differences ∆V
CC
are respected.
8. Thermal characteristics
[1] In compliance with JEDEC test board, in free air.
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
CCA
analog supply voltage
[1]
−0.5 +7.0 V
V
CCD
digital supply voltage
[1]
−0.5 +7.0 V
V
CCO
output supply voltage
[2]
−0.5 +5.0 V
∆V
CC
supply voltage difference V
CCA
− V
CCD
−1.0 +1.0 V
V
CCD
− V
CCO
−1.0 +4.0 V
V
CCA
− V
CCO
−1.0 +4.0 V
V
i(IN)
input voltage on pin IN referenced to AGND 0 V
CCA
+1 V
V
i(INN)
input voltage on pin INN referenced to AGND 0 V
CCA
+1 V
V
i(CLK)
input voltage on pin CLK referenced to DGND 0 V
CCD
+1 V
V
i(CLKN)
input voltage on pin CLKN referenced to DGND 0 V
CCD
+1 V
I
O
output current - 10 mA
T
stg
storage temperature −55 +150 °C
T
amb
ambient temperature −40 +85 °C
T
j
junction temperature - 150 °C
Table 4. Thermal characteristics
Symbol Parameter Conditions Typ Unit
R
th(j-a)
thermal resistance from junction to ambient
[1]
36.2 K/W
R
th(j-c)
thermal resistance from junction to case
[1]
14.3 K/W
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 6 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
9. Characteristics
Table 5. Characteristics
V
CCA
= 4.75 V to 5.25 V; V
CCD
= 4.75 V to 5.25 V; V
CCO
= 2.7 V to 3.6 V; AGND and DGND shorted together; T
amb
=
−
40
°
C
to +85
°
C; V
i(IN)
−
V
i(INN)
=
−
0.5 dBFS; V
ref(fs)
=V
CCA
−
1.87 V; V
I(cm)
=V
CCA
−
1.95 V; typical values measured at
V
CCA
=V
CCD
=5V, V
CCO
= 3.3 V, T
amb
=25
°
C and C
L
= 10 pF; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
V
CCA
analog supply voltage 4.75 5.0 5.25 V
V
CCD
digital supply voltage 4.75 5.0 5.25 V
V
CCO
output supply voltage 2.7 3.3 3.6 V
I
CCA
analog supply current - 120 135 mA
I
CCD
digital supply current - 50 65 mA
I
CCO
output supply current f
clk
= 80 MHz;
f
i
=93MHz
-1015mA
P
tot
total power dissipation f
clk
= 80 MHz; DC input - 840 990 mW
Clock inputs: pins CLK and CLKN
[1]
V
IL
LOW-level input voltage referenced to DGND; V
CCD
=5V
Positive
Emitter-Coupled
Logic (PECL) mode
3.19 - 3.52 V
Transistor-Transistor
Logic (TTL) mode
DGND - 0.8 V
V
IH
HIGH-level input voltage referenced to DGND; V
CCD
=5V
PECL mode 3.83 - 4.12 V
TTL mode 2.0 - V
CCD
V
I
IL
LOW-level input current V
CLK
or V
CLKN
= 3.52 V
[2]
-- 28µA
V
CLK
or V
CLKN
= 0.80 V 1 - - nA
I
IH
HIGH-level input current V
CLK
or V
CLKN
= 3.83 V - - 30 µA
V
CLK
or V
CLKN
= 2.00 V 2 - - nA
V
i(clk)dif
differential clock input
voltage
V
CLK
− V
CLKN
;
AC mode; DC voltage
level is 2.5 V
1.3 1.5 1.7 V
R
i
input resistance f
clk
=80MHz
[2]
- 6.3 - kΩ
C
i
input capacitance f
clk
=80MHz
[2]
- 1.1 - fF
Analog inputs: pins IN and INN
I
IL
LOW-level input current V
ref(fs)
=V
CCA
− 1.75 V - 5 - µA
I
IH
HIGH-level input current V
ref(fs)
=V
CCA
− 1.75 V - 5 - µA
R
i
input resistance
[2]
6.3 - - MΩ
C
i
input capacitance
[2]
- - 700 fF
V
I(cm)
common-mode input
voltage
V
i(IN)
=V
i(INN)
;
output code = 2047
V
CCA
− 2V
CCA
− 1.8 V
CCA
− 1.6 V
Digital inputs: pins OTC and CE_N
V
IL
LOW-level input voltage DGND - 0.3 × V
CCD
V
V
IH
HIGH-level input voltage 0.7 × V
CCD
-V
CCD
V
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

ADC1207S080HW/C1:5

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