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9DML0451AKILFT

P1-P3P4-P6P7-P9P10-P12P13-P13
DATASHEET
9DML04 REVISION A 06/06/16 1 ©2015 Integrated Device Technology, Inc.
2:4 3.3V PCIe Clock Mux 9DML04
Description
The 9DML04 devices are 3.3V members of IDT's
Full-Featured PCIe family. The 9DML04 supports PCIe
Gen1-4 Common Clocked (CC), Separate Reference no
Spread (SRnS), and Separate Reference Independent
Spread (SRIS) architectures. The part provides a choice of
asynchronous and glitch-free switching modes, and offers a
choice of integrated output terminations providing direct
connection to 85 or 100 transmission lines. The
9DML04P1 can be factory programmed with a user-defined
power up default SMBus configuration.
Recommended Application
Servers, ATCA, ATE, Master/Slave applications
Output Features
• 4 – 1~200 MHz Low-Power HCSL (LP-HCSL) DIF pairs
• 9DML0441 default ZOUT = 100
• 9DML0451 default ZOUT = 85
• 9DML04P1 factory programmable defaults
Key Specifications
• PCIe Gen1-2-3-4 CC compliant
• PCIe Gen2-3 SRIS compliant
• DIF additive cycle-to-cycle jitter <1ps
• DIF output-to-output skew <50ps
• Additive phase jitter is <0.1ps rms for PCIe
• Additive phase jitter 160fs rms typ. @156.25M (1.5M to
10M)
Features/Benefits
• Direct connection to 100 (xx41) or 85 (xx51)
transmission lines; saves 16 resistors compared to
standard PCIe devices
• 76mW typical power consumption; eliminates thermal
concerns
• Spread Spectrum (SS) compatible; allows SS for EMI
reduction
• Customer defined power up default can be factory
programmed into P1 device; allows exact optimization to
customer requirements:
• control input polarity
• control input pull up/downs
• slew rate for each output
• differential output amplitude
• output impedance for each output
• OE# pins; support DIF power management
• HCSL-compatible differential inputs; can be driven by
common clock source
• Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power up even if both inputs are
not running, then transition to glitch-free switching mode
• Space saving 24-pin 4x4mm VFQFPN; minimal board
space
Block Diagram
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
DIF0
DIF1
DIF2
DIF3
A
B
4
^OE(3:0)#
DIF_INA
DIF_INB
vSW_MODE
^SEL_A_B#
2:4 3.3V PCIE CLOCK MUX 2 REVISION A 06/06/16
9DML04 DATASHEET
Pin Configuration
Power Management Table
Power Connections
GNDR
^SEL_A_B#
^OE3#
DIF3#
DIF3
^OE2#
24 23 22 21 20 19
DIF_INA 1
18
DIF2#
DIF_INA# 2
17
DIF2
VDDR3.3 3
16
VDD3.3
VDDR3.3 4
15
GND
DIF_INB
5
14
DIF1#
DIF_INB# 6 13 DIF1
7 8 9 101112
GNDR
vSW_MODE
^OE0#
DIF0
DIF0#
^OE1#
24 VFQFPN, 4x4 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
v prefix indicates internal 120KOhm pull down resistor
9DML04xx
Connect ePad
to GND
True O/P Comp. O/P
0 Running Running Running
1 Running Low Low
DIF_INOEx# Pin
DIFx
VDD GND
324
47
16 15 DIF outputs
Description
Pin Number
Input A receiver analo
g
Input B receiver analo
g
REVISION A 06/06/16 3 2:4 3.3V PCIE CLOCK MUX
9DML04 DATASHEET
Pin Descriptions
Pin# Pin Name Type Pin Description
1 DIF_INA IN HCSL Differential True input
2 DIF_INA# IN HCSL Differential Complement Input
3 VDDR3.3 PWR
3.3V power for differential input clock (receiver). This VDD should be treated
as an Analog power rail and filtered appropriately.
4 VDDR3.3 PWR
3.3V power for differential input clock (receiver). This VDD should be treated
as an Analog power rail and filtered appropriately.
5 DIF_INB IN HCSL Differential True input
6 DIF_INB# IN HCSL Differential Complement Input
7 GNDR GND Analog Ground pin for the differential input (receiver)
8vSW_MODE IN
Switch Mode. This pin selects either asynchronous or glitch-free switching of
the mux. Use asynchronous mode if 0 or 1 of the input clocks is running.
Use glitch-free mode if both input clocks are running. This pin has an internal
pull down resistor of ~120kohms.
0 = asynchronous mode
1 = glitch-free mode
9^OE0# IN
Active low input for enabling DIF pair 0. This pin has an internal pull-up
resistor.
1 =disable outputs, 0 = enable outputs
10 DIF0 OUT Differential true clock output
11 DIF0# OUT Differential Complementary clock output
12 ^OE1# IN
Active low input for enabling DIF pair 1. This pin has an internal pull-up
resistor.
1 =disable outputs, 0 = enable outputs
13 DIF1 OUT Differential true clock output
14 DIF1# OUT Differential Complementary clock output
15 GND GND Ground pin.
16 VDD3.3 PWR Power supply, nominal 3.3V
17 DIF2 OUT Differential true clock output
18 DIF2# OUT Differential Complementary clock output
19 ^OE2# IN
Active low input for enabling DIF pair 2. This pin has an internal pull-up
resistor.
1 =disable outputs, 0 = enable outputs
20 DIF3 OUT Differential true clock output
21 DIF3# OUT Differential Complementary clock output
22 ^OE3# IN
Active low input for enabling DIF pair 3. This pin has an internal pull-up
resistor.
1 =disable outputs, 0 = enable outputs
23 ^SEL_A_B# IN
Input to select differential input clock A or differential input clock B. This
input has an internal pull-up resistor.
0 = Input B selected, 1 = Input A selected.
24 GNDR GND Analog Ground pin for the differential input (receiver)
25 EPAD GND Connect to Ground.
P1-P3P4-P6P7-P9P10-P12P13-P13

9DML0451AKILFT

Mfr. #:
Buy 9DML0451AKILFT
Manufacturer:
IDT
Description:
Clock Buffer 2:4 LP-HCSL CLOCK MUX ZO=85OHM
Lifecycle:
New from this manufacturer.
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