2:4 3.3V PCIE CLOCK MUX 8 REVISION A 06/06/16
9DML04 DATASHEET
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common Clocked
(CC) Architectures
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Separate
Reference Independent Spread (SRIS) Architectures
5
Electrical Characteristics– Unfiltered Phase Jitter Parameters
T
AMB
= over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
INDUSTRY
LIMIT
UNITS Notes
t
jphPCIeG1-CC
PCIe Gen 1 0.0 0.01
ps
(p-p)
1,2,3,5
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
0.0 0.01
ps
(rms)
1,2,4,5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
0.0 0.01
ps
(rms)
1,2,4,5
t
jphPCIeG3-CC
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
0.0 0.01
ps
(rms)
1,2,4,5
t
jphPCIeG4-CC
PCIe Gen 4
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
0.0 0.01
ps
(rms)
1,2,4,5
1
Applies to all outputs.
5
Driven by 9FGL0841 or equivalent
Additive Phase Jitter n/a
t
jphPCIeG2-CC
2
Based on PCIe Base Specification Rev4.0 version 0.7draft. See http://www.pcisig.com for latest specifications.
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
For RMS values additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2 ] where a is rms input jitter and c is rms total
T
AMB
= over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
INDUSTRY
LIMIT
UNITS Notes
t
jphPCIeG2-
SRIS
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
0.0 0.01
ps
(rms)
1,2,4
t
jphPCIeG3-
SRIS
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
0.0
0.01
ps
(rms)
1,2,4
1
Applies to all outputs.
Additive Phase Jitter n/a
2
Based on PCIe Base Specification Rev3.1a. These filters are different than Common Clock filters. See http://www.pcisig.com for latest
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
For RMS values, additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2 ] where a is rms input jitter and c is rms total
5
As of PCIe Base Specification Rev4.0 draft 0.7, SRIS is not currently defined for Gen1 or Gen4.
TA = T
AMB,
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
INDUSTRY
LIMIT UNITS Notes
t
jph156M
156.25MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
159 N/A
fs
(rms)
1,2,3
t
jph156M12k-
20
156.25MHz, 12kHz to 20MHz, -20dB/decade
rollover <12kHz, -40db/decade rolloff > 20MHz
363 N/A
fs
(rms)
1,2,3
1
Guaranteed by design and characterization, not 100% tested in production.
3
For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
2
Driven by Rohde&Schartz SMA100
Additive Phase Jitter,
Fanout Mode
