AD1674
REV. C
–6–
ORDERING GUIDE
INL S/(N+D) Package Package
Model
1
Temperature Range (T
MIN
to T
MAX
)(T
MIN
to T
MAX
) Description Option
2
AD1674JN 0°C to +70°C ±1 LSB 69 dB Plastic DIP N-28
AD1674KN 0°C to +70°C ±1/2 LSB 70 dB Plastic DIP N-28
AD1674JR 0°C to +70°C ±1 LSB 69 dB Plastic SOIC R-28
AD1674KR 0°C to +70°C ±1/2 LSB 70 dB Plastic SOIC R-28
AD1674AR –40°C to +85°C ±1 LSB 69 dB Plastic SOIC R-28
AD1674BR –40°C to +85°C ±1/2 LSB 70 dB Plastic SOIC R-28
AD1674AD –40°C to +85°C ±1 LSB 69 dB Ceramic DIP D-28
AD1674BD –40°C to +85°C ±1/2 LSB 70 dB Ceramic DIP D-28
AD1674TD –55°C to +125°C ±1 LSB 70 dB Ceramic DIP D-28
NOTES
1
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current
AD1674/883B data sheet. SMD is also available.
2
N = Plastic DIP; D = Hermetic Ceramic DIP; R = Plastic SOIC.
TIMING—STAND-ALONE MODE (Figures 4a and 4b)
J, K, A, B Grades T Grade
Parameter Symbol Min Typ Max Min Typ Max Units
Data Access Time t
DDR
150 150 ns
Low R/
C Pulse Width t
HRL
50 50 ns
STS Delay from R/
C t
DS
200 225 ns
Data Valid After R/
C Low t
HDR
25 25 ns
STS Delay After Data Valid t
HS
0.6 0.8 1.2 0.6 0.8 1.2 µs
High R/C Pulse Width t
HRH
150 150 ns
NOTE
All min and max specifications are guaranteed.
Specifications subject to change without notice.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1674 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
DATA
VALID
DATA VALID
HIGH-Z
STS
DB11 – DB0
R/C
_
t
HRL
t
DS
t
C
t
HS
t
HDR
Figure 4a. Stand-Alone Mode Timing Low Pulse for R/
C
DATA
VALID
HIGH-Z
HIGH-Z
STS
DB11 – DB0
R/C
_
t
HRH
t
DS
t
C
t
DDR
t
HDR
t
HL
Figure 4b. Stand-Alone Mode Timing High Pulse for R/
C
ABSOLUTE MAXIMUM RATINGS*
V
CC
to Digital Common . . . . . . . . . . . . . . . . . . . 0 to + 16.5 V
V
EE
to Digital Common . . . . . . . . . . . . . . . . . . . . . 0 to –16.5 V
V
LOGIC
to Digital Common . . . . . . . . . . . . . . . . . . 0 V to +7 V
Analog Common to Digital Common . . . . . . . . . . . . . . . ±1 V
Digital Inputs to Digital Common . . . –0.5 V to V
LOGIC
+0.5 V
Analog Inputs to Analog Common . . . . . . . . . . . . V
EE
to V
CC
20 V
IN
to Analog Common . . . . . . . . . . . . . . . . . V
EE
to +24 V
REF OUT . . . . . . . . . . . . . . . . . Indefinite Short to Common
. . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to V
CC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . .825 mW
Lead Temperature, Soldering (10 sec) . . . . . . . +300°C, 10 sec
Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
AD1674
REV. C
–7–
PIN DESCRIPTION
Symbol Pin No. Type Name and Function
AGND 9 P Analog Ground (Common).
A
0
4 DI Byte Address/Short Cycle. If a conversion is started with A
0
Active LOW, a full 12-bit conversion
cycle is initiated. If A
0
is Active HIGH during a convert start, a shorter 8-bit conversion cycle
results. During Read (R/
C = 1) with 12/8 LOW, A
0
= LOW enables the 8 most significant bits
(DB4–DB11), and A
0
= HIGH enables DB3–DB0 and sets DB7–DB4 = 0.
BIP OFF 12 AI Bipolar Offset. Connect through a 50 resistor to REF OUT for bipolar operation or to Analog
Common for unipolar operation.
CE 6 DI Chip Enable. Chip Enable is Active HIGH and is used to initiate a convert or read operation.
CS 3 DI Chip Select. Chip Select is Active LOW.
DB11–DB8 27–24 DO Data Bits 11 through 8. In the 12-bit format (see 12/
8 and A
0
pins), these pins provide the up-
per 4 bits of data. In the 8-bit format, they provide the upper 4 bits when A
0
is LOW and are
disabled when A
0
is HIGH.
DB7–DB4 23–20 DO Data Bits 7 through 4. In the 12-bit format these pins provide the middle 4 bits of data. In the
8-bit format they provide the middle 4 bits when Ao is LOW and all zeroes when A
0
is HIGH.
DB3–DB0 19–16 DO Data Bits 3 through 0. In the 12-bit format these pins provide the lower 4 bits of data. In the
8-bit format these pins provide the lower 4 bits of data when A
0
is HIGH, they are disabled
when A
0
is LOW.
DGND 15 P Digital Ground (Common).
REF OUT 8 AO +10 V Reference Output.
R/
C 5 DI Read/Convert. In the full control mode R/C is Active HIGH for a read operation and Active LOW
for a convert operation. In the stand-alone mode, the falling edge of R/
C initiates a conversion.
REF IN 10 AI Reference Input is connected through a 50 resistor to +10 V Reference for normal operation.
STS 28 DO Status is Active HIGH when a conversion is in progress and goes LOW when the conversion is
completed.
V
CC
7 P +12 V/+15 V Analog Supply.
V
EE
11 P –12 V/–15 V Analog Supply.
V
LOGIC
1 P +5 V Logic Supply.
10 V
IN
13 AI 10 V Span Input, 0 V to +10 V unipolar mode or –5 V to +5 V bipolar mode. When using the
AD1674 in the 20 V Span 10 V
IN
should not be connected.
20 V
IN
14 AI 20 V Span Input, 0 V to +20 V unipolar mode or –10 V to +10 V bipolar mode. When using
the AD1674 in the 10 V Span 20 V
IN
should not be connected.
12/
8 2 DI The 12/8 pin determines whether the digital output data is to be organized as two 8-bit words
(12/8 LOW) or a single 12-bit word (12/8 HIGH).
TYPE: AI = Analog Input
AO = Analog Output
DI = Digital Input
DO = Digital Output
P = Power
FUNCTIONAL BLOCK DIAGRAM
REF OUT
SHA
COMP
20k
10k
5k
2.5k
2.5k
5k
12
12
AD1674
AGND
BIP OFF
REF IN
20V
IN
10V
IN
IDAC
12
CONTROL
CE
12/8
CS
R/C
A
0
5k
10k
SAR
CLOCK
10V
REF
REGISTERS / 3-STATE OUTPUT BUFFERS
DAC
STS
DB11 (MSB)
DB0 (LSB)
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
AD1674
18
28
27
24
23
22
26
25
21
20
19
17
16
15
13
1
2
5
6
7
3
4
8
9
10
12
14
V
LOGIC
CE
V
CC
A
0
REF OUT
AGND
REF IN
V
EE
BIP OFF
10V
IN
20V
IN
CS
12/8
R/C
STS
DB11(MSB)
DB8
DB7
DB6
DB10
DB9
DB5
DB4
DB3
DB2
DB1
DB0(LSB)
DGND
11
AD1674
REV. C
–8–
DEFINITION OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
The ideal transfer function for an ADC is a straight line drawn
between “zero” and “full scale.” The point used as “zero”
occurs 1/2 LSB before the first code transition. “Full scale” is
defined as a level 1 1/2 LSB beyond the last code transition.
Integral nonlinearity is the worst-case deviation of a code from
the straight line. The deviation of each code is measured from
the middle of that code.
DIFFERENTIAL NONLINEARITY (DNL)
A specification which guarantees no missing codes requires that
every code combination appear in a monotonic increasing
sequence as the analog input level is increased. Thus every code
must have a finite width. The AD1674 guarantees no missing
codes to 12-bit resolution; all 4096 codes are present over the
entire operating range.
UNIPOLAR OFFSET
The first transition should occur at a level 1/2 LSB above ana-
log common. Unipolar offset is defined as the deviation of the
actual transition from that point at 25°C. This offset can be
adjusted as shown in Figure 11.
BIPOLAR OFFSET
In the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1/2 LSB
below analog common. The bipolar offset error specifies the
deviation of the actual transition from that point at 25°C. This
offset can be adjusted as shown in Figure 12.
FULL-SCALE ERROR
The last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1/2 LSB below the nominal
full scale (9.9963 volts for 10 volts full scale). The full-scale
error is the deviation of the actual level of the last transition
from the ideal level at 25°C. The full-scale error can be adjusted
to zero as shown in Figures 11 and 12.
TEMPERATURE DRIFT
The temperature drifts for full-scale error, unipolar offset and
bipolar offset specify the maximum change from the initial
(25°C) value to the value at T
MIN
or T
MAX
.
POWER SUPPLY REJECTION
The effect of power supply error on the performance of the
device will be a small change in full scale. The specifications
show the maximum full-scale change from the initial value with
the supplies at various limits.
FREQUENCY-DOMAIN TESTING
The AD1674 is tested dynamically using a sine wave input and
a 2048 point Fast Fourier Transform (FFT) to analyze the
resulting output. Coherent sampling is used, wherein the ADC
sampling frequency and the analog input frequency are related
to each other by a ratio of integers. This ensures that an integral
multiple of input cycles is captured, allowing direct FFT pro-
cessing without windowing or digital filtering which could mask
some of the dynamic characteristics of the device. In addition,
the frequencies are chosen to he “relatively prime” (no common
factors) to maximize the number of different ADC codes that
are present in a sample sequence. The result, called Prime
Coherent Sampling, is a highly accurate and repeatable measure
of the actual frequency-domain response of the converter.
NYQUIST FREQUENCY
An implication of the Nyquist sampling theorem, the “Nyquist
Frequency” of a converter is that input frequency which is one-
half the sampling frequency of the converter.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO
S/(N+D) is the ratio of the rms value of the measured input sig-
nal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of a full-scale input signal and is ex-
pressed as a percentage or in decibels. For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m+n), at sum and difference frequencies of mfa ± nfb,
where m, n = 0, 1, 2, 3. . . . Intermodulation terms are those for
which m or n is not equal to zero. For example, the second
order terms are (fa + fb) and (fa – fb) and the third order terms
are (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). The IMD
products are expressed as the decibel ratio of the rms sum of the
measured input signals to the rms sum of the distortion terms.
The two signals are of equal amplitude and the peak value of
their sums is –0.5 dB from full scale. The IMD products are
normalized to a 0 dB input signal.
FULL-POWER BANDWIDTH
The full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
FULL-LINEAR BANDWIDTH
The full-linear bandwidth is the input frequency at which the
slew rate limit of the sample-hold-amplifier (SHA) is reached.
At this point, the amplitude of the reconstructed fundamental
has degraded by less than –0.1 dB. Beyond this frequency, dis-
tortion of the sampled input signal increases significantly.
APERTURE DELAY
Aperture delay is a measure of the SHA’s performance and is
measured from the falling edge of Read/Convert (R/
C) to when
the input signal is held for conversion.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.

AD1674AR-REEL

Mfr. #:
Manufacturer:
Description:
Analog to Digital Converters - ADC 12-Bit 100 kSPS Complete IC
Lifecycle:
New from this manufacturer.
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