3-WIRE SERIAL E
2
PROM
S-93C76A
Rev.7.0
_00
Seiko Instruments Inc.
10
Initial Shipment Data
Initial shipment data off all adresses is “FFFFh”.
Operation
All instructions are executed by making CS “H” and then inputting DI at the rising edge of the SK pulse. An instruction
is input in the order of its start bit, instruction, address, and data. The start bit is recognized when “H” of DI is input at
the rising edge of SK after CS has been made “H”. As long as DI remains “L”, therefore, the start bit is not recognized
even if the SK pulse is input after CS has been made “H”. The SK clock input while DI is “L” before the start bit is input
is called a dummy clock. By inserting as many dummy clocks as required before the start bit, the number of clocks the
internal serial interface of the CPU can send out and the number of clocks necessary for operation of the serial memory
IC can be adjusted. Inputting the instruction is complete when CS is made “L”. CS must be made “L” once during the
period of t
CDS
in between instructions.
“L” of CS indicates a standby status. In this status, input of SK and DI is invalid, and no instruction is accepted.
1. Reading (READ)
The READ instruction is used to read the data at a specified address. When this instruction is executed, the
address A
0
is input at the rising edge of SK and the DO pin, which has been in a high-impedance (High-Z) state,
outputs “L”. Subsequently, 16 bits of data are sequentially output at the rising edge of SK.
If SK is output after the 16-bit data of the specified address has been output, the address is automatically
incremented, and the 16-bit data of the next address is then output. By inputting SK sequentially with CS kept at
“H”, the data of the entire memory space can be read. When the address is incremented from the last address (A
8
… A
1
A
0
= 1 … 1 1), it returns to the first address (A
8
… A
1
A
0
= 0 … 0 0).
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
+1 A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
+2
CS
1 3 4 5 6 7 8 9
10 11 12 13 14 15 16
2
26 27 28 29 30 31 42 43 44 45 46 32 48
SK
1 1 X 0
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DI
0
D
15
D
14
D
13
D
15
D
14
D
13
D
2
D
1
D
0
D
15
D
14
D
13
D
2
D
1
D
0
High-Z
DO
High-Z
47
Figure 6 Read Timing
3-WIRE SERIAL E
2
PROM
Rev.7.0
_00
S-93C76A
Seiko Instruments Inc.
11
2. Writing (WRITE, ERASE, WRAL, ERAL)
Write instructions (WRITE, ERASE, WRAL, and ERAL) are used to start writing data to the non-volatile memory by
making CS “L” after the specified number of clocks has been input.
The write operation is completed within the write time t
PR
(10 ms) no matter which write instruction is used. The
typical write time is less than half 10 ms. If the end of the write operation is known, therefore, the write cycle can
be minimized. To ascertain the end of a write operation, make CS “L” to start the write operation and then make
CS “H” again to check the status of the DO output pin. This series of operations is called a verify operation.
If DO outputs “L” during the verify operation period in which CS is “H”, it indicates that a write operation is in
progress. If DO outputs “H”, it indicates that the write operation is finished. The verify operation can be executed
as many times as required. This operation can be executed in two ways. One is detecting the positive transition
of DO output from “L” to “H” while holding CS at “H”. The other is detecting the positive transition of DO output
from “L” to “H” by making CS “H” once and checking DO output, and then returning CS to “L”.
During the write period, SK and DI are invalid. Do not input any instructions during this period. Input an
instruction while the DO pin is outputting “H” or is in a high-impedance state. Even while the DO pin is outputing
“H”, DO immediately goes into a high-impedance (High-Z) state if “H” of DI (start bit) is input at the rising edge of
SK.
Keep DI “L” during the verify operation period.
2. 1 Writing data (WRITE)
This instruction is used to write 16-bit data to a specified address.
After making CS “H”, input a start bit, the WRITE instruction, an address, and 16-bit data. If data of more than
16 bits is input, the written data is sequentially shifted at each clock, and the 16 bits input last are the valid
data. The write operation is started when CS is made “L”. It is not necessary to set data to “1” before it is
written.
DO
<1>
2 3
4
5
6
7 8 9 10 11 12 13 14 29
0 1 X A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D0
DI
SK
CS
High-Z
t
CDS
t
SV
t
PR
b
usy
r
ead
y
Standby
High-Z
t
HZ1
Verify
1
Figure 7 Data Write Timing
2. 2 Erasing data (ERASE)
This instruction is used to erase specified 16-bit data. All the 16 bits of the data are “1”. After making CS
“H”, input a start bit, the ERASE instruction, and an address. It is not necessary to input data. The data
erase operation is started when CS is made “L”.
DO
<1>
2 3
4
5
6
7 8 9 10 11 12 13
1 1 X A8 A7 A6 A5 A4 A3 A2 A1 A0
DI
SK
CS
High-Z
t
CDS
t
SV
t
PR
b
usy
r
ead
y
Standby
High-Z
t
HZ1
Verify
1
Figure 8 Data Erase Timing
3-WIRE SERIAL E
2
PROM
S-93C76A
Rev.7.0
_00
Seiko Instruments Inc.
12
2. 3 Writing to chip (WRAL)
This instruction is used to write the same 16-bit data to the entire address space of the memory.
After making CS “H”, input a start bit, the WRAL instruction, an address, and 16-bit data. Any address may be
input. If data of more than 16 bits is input, the written data is sequentially shifted at each clock, and the 16-bit
data input last is the valid data. The write operation is started when CS is made “L”. It is not necessary to
set the data to “1” before it is written.
DO
<1>
2 3
4
5
6
7 8 9 10 11 12 13 14 29
0 0 0 1 D15 D0
DI
SK
CS
High-Z
t
CDS
t
SV
t
PR
b
usy
r
ead
y
Standby
High-Z
t
HZ1
Verify
1
8Xs
Figure 9 Chip Write Timing
2. 4 Erasing chip (ERAL)
This instruction is used to erase the data of the entire address space of the memory.
All the data is “1”. After making CS “H”, input a start bit, the ERAL instruction, and an address. Any address
may be input. It is not necessary to input data. The chip erase operation is started when CS is made “L”.
DO
<1>
2 3
4
5
6
7 8 9 10 11 12 13
0 0 1 0
DI
SK
CS
High-Z
t
CDS
t
SV
t
PR
b
usy
r
eady
Standby
High-Z
t
HZ1
Verif
y
1
8Xs
Figure 10 Chip Erase Timing

S-93C76AFM-TF-U

Mfr. #:
Manufacturer:
ABLIC
Description:
EEPROM MICROWIRE EEPROM
Lifecycle:
New from this manufacturer.
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