3-WIRE SERIAL E
2
PROM
Rev.7.0
_00
S-93C76A
Seiko Instruments Inc.
13
3. Write enable (EWEN) and write disable (EWDS)
The EWEN instruction is used to enable a write operation. The status in which a write operation is enabled is
called the program-enabled mode.
The EWDS instruction is used to disable a write operation. The status in which a write operation is disabled is
called the program-disabled mode.
The write operation is disabled upon power application and detection of a low supply voltage. To prevent an
unexpected write operation due to external noise or a CPU malfunctions, it should be kept in write disable mode
except when performing write operations, after power-on and before shutdown.
<1>
2
3
4 5 6 7 8 9 10 11 12 13
DI
SK
CS
11 = EWEN
00 = EWDS
Standb
y
1
8Xs
0 0
Figure 11 Write Enable / Disable Timing
Start Bit
A start bit is recognized by latching the high level of DI at the rising edge of SK after changing CS to high (start bit
recognition). A write operation begins by inputting the write instruction and setting CS to low. Subsequently, by setting
CS to high again, the DO pin outputs a low level if the write operation is still in progress and a high level if the write
operation is complete (verify operation). Therefore, only after a write operation, in order to input the next command, CS
is set to high, which switches the DO pin from a high-impedance state (High-Z) to a data output state. However, if start
bit is recognized, the DO pin returns to the high-impedance state (refer to Figure 5 Timing Chart).
Make sure that data output from the CPU does not interfere with the data output from the serial memory IC when
configuring a 3 -wire interface by connecting the DI input pin and DO output pin, as such interference may cause a start
bit fetch problem. Take the measures described in “ 3-Wire Interface (Direct Connection between DI and DO)”.
3-WIRE SERIAL E
2
PROM
S-93C76A
Rev.7.0
_00
Seiko Instruments Inc.
14
Write Protect Function during the Low Power Supply Voltage
The S-93C76A provides a built-in detector to detect a low power supply voltage and disable writing. When the power
supply voltage is low or at power application, the write instructions (WRITE, ERASE, WRAL, and ERAL) are cancelled,
and the write disable state (EWDS) is automatically set. The detection voltage is 1.75 V typ., the release voltage is
2.05 V typ., and there is a hysteresis of about 0.3 V (refer to Figure 12). Therefore, when a write operation is
performed after the power supply voltage has dropped and then risen again up to the level at which writing is possible,
a write enable instruction (EWEN) must be sent before a write instruction (WRITE, ERASE, WRAL, or ERAL) is
executed.
When the power supply voltage drops during a write operation, the data being written to an address at that time is not
guaranteed.
Release voltage (+V
DET
)
2.05 V typ.
Power supply voltage
Hysteresis
About 0.3 V
Detection voltage (V
DET
)
1.75 V typ.
Write instruction cancelled
Write disable state (EWDS) automatically set
Figure 12 Operation during Low Power Supply Voltage
3-WIRE SERIAL E
2
PROM
Rev.7.0
_00
S-93C76A
Seiko Instruments Inc.
15
3-Wire Interface (Direct Connection between DI and DO)
There are two types of serial interface configurations: a 4-wire interface configured using the CS, SK, DI, and DO pins,
and a 3-wire interface that connects the DI input pin and DO output pin.
When the 3-wire interface is employed, a period in which the data output from the CPU and the data output from the
serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect the DI and DO pins
of the S-93C76A via a resistor (10 kΩ to 100 kΩ) so that the data output from the CPU takes precedence in being input
to the DI pin (refer to Figure 13).
CPU
DI
SIO
DO
S-93C76A
R: 10 kΩ to 100 kΩ
Figure 13 Connection of 3-Wire Interface
Input Pin and Output Pin
1. Connection of input pins
All the input pins of the S-93C76A employ a CMOS structure, so design the equipment so that high impedance will
not be input while the S-93C76A is operating. Especially, deselect the CS input (a low level) when turning on / off
power and during standby. When the CS pin is deselected (a low level), incorrect data writing will not occur.
Connect the CS pin to GND via a resistor (10 kΩ to 100 kΩ pull-down resistor). To prevent malfunction, it is
recommended to use equivalent pull-down resistors for pins other than the CS pin.
2. Equivalent circuit of input and output pin
The following shows the equivalent circuits of input pins of the S-93C76A. None of the input pins incorporate pull-
up and pull-down elements, so special care must be taken when designing to prevent a floating status.
Output pins are high-level / low-level / high-impedance tri-state outputs. The TEST pin is disconnected from the
internal circuit by a switching transistor during normal operation. As long as the absolute maximum rating is
satisfied, the TEST pin and internal circuit will never be connected.

S-93C76AFM-TF-U

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Manufacturer:
ABLIC
Description:
EEPROM MICROWIRE EEPROM
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