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ICS-43432

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
ICS-43432
THEORY OF OPERATION
POWER MANAGEMENT
The ICS-43432 has two power states: normal operation, and standby mode.
Startup and Normal Operation
The ICS-43432 will begin to output non-zero data 4462 SCK clock cycles (1.5 ms with f
SCK
= 3.072 MHz) after initial power-up. The part
is in normal operation mode when SCK and WS are active.
Table 7 shows the startup time for different sampling rates.
Table 7. Startup time
f
S
(WS frequency)
Startup time
48 kHz
1.5 ms
24 kHz
3.0 ms
16 kHz
4.5 ms
8 kHz
9.0 ms
Standby Mode
The microphone enters standby mode when the frequency of SCK falls below about 1 kHz. It is recommended to enter standby
mode by stopping both the SCK and WS clock signals and pulling those signals to ground to avoid drawing current through the WS
pin’s internal pull-down resistor. The timing for exiting standby mode is the same as normal startup.
It is not recommended to supply active clocks (WS and SCK) to the ICS-43432 while there is no power supplied to VDD, doing this
continuously turns on ESD protection diodes, which may affect long-term reliability of the microphone.
Soft Unmute
The ICS-43432 has a soft unmute feature to prevent pops on power-up. From the time that the ICS-43432 starts to output data, the
volume will ramp up to the full-scale output level over 256 WS clock cycles. With a 48 kHz sampling rate, this unmute sequence will
take about 5.3 ms.
SYNCHRONIZING MICROPHONES
Stereo ICS-43432 microphones are synchronized by the WS signal, so audio captured from two microphones sharing the same clock
will be in sync. If the mics are enabled separately, this synchronization may take up to 0.35 ms after the enable signal is asserted
while internal data paths are flushed.
I²S DATA INTERFACE
The slave serial data port’s format is I²S, 24-bit, twos complement. There must be 64 SCK cycles in each WS stereo frame. The L/R
control pin determines whether the ICS-43432 outputs data in the left or right channel. When set to the left channel, the data will be
output following WS’s falling edge and when set to output on the right channel, data will be output following WS’s rising edge.
For a stereo application, the SD pins of the left and right ICS-43432 microphones should be tied together as shown in Figure 10. The
format of a stereo I²S data stream is shown in Figure 11. Figure 12 and Figure 13 show the formats of a mono microphone data
stream for left and right microphones, respectively.
Data Output Mode
The output data pin (SD) is tri-stated when it is not actively driving I²S output data. SD immediately tristates after the LSB
is output so that another microphone can drive the common data line.
Page 10 of 20
Document Number: DS-000038
Revision: 1.0
ICS-43432
The SD trace should have a pulldown resistor to discharge the line during the time that all microphones on the bus have tri-stated
their outputs. A 100 kΩ resistor is sufficient for this, as shown in Figure 10. If the SD line needs to be discharged faster than a 100 kΩ
resistor can, a smaller resistor, such as 10 kΩ, can be used.
Data Word Length
The output data word length is 24 bits per channel.
Data Word Format
The default data format is I²S (twos complement), MSB-first. In this format, the MSB of each word is delayed by one SCK cycle from
the start of each half-frame.
Figure 10. System Block Diagram
Figure 11. Stereo Output I²S Format
Figure 12. Mono Output I²S Format Left Channel (LR = 0)
Figure 13. Mono Output I²S Format Right Channel (LR = 1)
SCK
WS
SD
SYSTEM MA
ST
ER
(DSP, MICROCON
T
RO
LLE
R
,
CODEC)
SCK
WS
CONFIG SD
VDD
L
EF
T
ICS-43432
GND
0
.1
µF
F
RO
M VO
LT
A
GE
R
EGUL ATOR
(1.8VTO 3.3V)
LRSCK
WS
CONFIG
SD
VDD
R
IGH
T
ICS-43432
G
ND
0
.1
µ
F
100kΩ
V
D
D
LR
MSB LSB
LEFT CHANNEL
MSB LSB
RIGHT CHANNELHIGH-Z HIGH-Z HIGH-Z
1 2 3 4 24 25 26 32 33 34 35 36 56 57 58 64
WS
SCK (64 × f
S
)
SD (24-BIT)
MSB LSB
LEFT CHANNEL
HIGH-Z
HIGH-Z
1 2 3 4 24 25
26 32 33 34 35 36
56 57 58 64
W
S
SCK (64 × f
S
)
SD (24-BIT)
MSB LSB
RIGHT CHANNELHIGH-Z HIGH-Z
1 2 3 4 24 25 26 32 33 34 35 36 56 57 58 64
WS
SCK (64 × f
S
)
SD (24-BIT)
Page 11 of 20
Document Number: DS-000038
Revision: 1.0
ICS-43432
Data Output Format
The output data word length is 24 bits/channel. The data word format is 2’s complement, MSB first.
The output data pin (SD) is tri-stated when it is not actively driving output data. SD will immediately tri-state after the LSB is output
so that another microphone can drive the common data line.
DIGITAL MICROPHONE SENSITIVITY
The sensitivity of a digital output microphone is specified in units of dB FS (decibels relative to a full-scale digital output). A 0 dB FS
sine wave is defined as a signal whose peak just touches the full-scale code of the digital word (see Figure 5). This measurement
convention means that signals with a different crest factor may have an RMS level higher than 0 dB FS. For example, a full-scale
square wave has an RMS level of 3 dB FS.
Figure 11. 1 kHz, 0 dB FS Sine Wave
The definition of a 0 dB FS signal must be understood when measuring the sensitivity of the ICS-43432. An acoustic input signal of a
1 kHz sine wave at 94 dB SPL applied to the ICS-43432 results in an output signal with a −26 dB FS level. This means that the output
digital word peaks at −26 dB below the digital full-scale level. A common misunderstanding is that the output has an RMS level of
−29 dB FS; however, this is not the case because of the definition of a 0 dB FS sine wave.
There is no commonly accepted unit of measurement to express the instantaneous level of a digital signal output from the
microphone, as opposed to the RMS level of the signal. Some measurement systems express the instantaneous level of an individual
sample in units of D, where 1.0 D is digital full scale (see Figure 11). In this case, a −26 dB FS sine wave has peaks at 0.05 D.
For more information about digital microphone sensitivity, see the AN-1112 Application Note, Microphone Specifications Explained.
DIGITAL FILTER CHARACTERISTICS
The ICS-43432 has an internal digital bandpass filter. A high-pass filter eliminates unwanted low frequency signals. A low-pass
decimation filter scales the pass band with the sampling frequency and performs required out-of-band noise reduction.
High-Pass Filter
The ICS-43432 incorporates a high-pass filter to remove unwanted dc and very low frequency components. With f
S
= 48 kHz, this high
pass filter has a −3 dB corner frequency of 3.7 Hz. The cutoff frequency scales with changes in sampling rate.
This digital filter response is in addition to the acoustic high-pass response of the ICS-43432 that has a −3 dB corner of 50 Hz.
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 0.9 1.00.80.70.60.50.40.30.20.1
DIGITAL AMPLITUDE (D)
TIME (ms)
Page 12 of 20
Document Number: DS-000038
Revision: 1.0
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ICS-43432

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TDK InvenSense
Description:
MIC MEMS DIGITAL I2S OMNI -26DB
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