LTM4623
13
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applicaTions inForMaTion
The LTM4623 device is an inherently current mode con-
trolled device, so parallel modules will have very good
current sharing. This will balance the thermals
on the
design. Please tie the RUN, TRACK/SS, FB and COMP pins
of each paralleling module together. Figure 26 shows an
example of parallel operation and pin connection.
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current can
-
cellation mathematical derivations are presented, and a
graph is displayed representing the RMS ripple current
reduction as a function of the number of interleaved phases.
Figure3 shows this graph.
Soft-Start And Output V
oltage Tracking
The TRACK/SS pin provides a means to either soft start
the regulator or track it to a different power supply. A
capacitor on the TRACK/SS pin will program the ramp
rate of the output voltage. An internal 2µA current source
will charge up the external soft-start capacitor towards
INTV
CC
voltage. When the TRACK/SS voltage is below
0.6V, it will take over the internal 0.6V reference voltage
to control the output voltage. The total soft-start time can
be calculated as:
t
SS
= 0.6
C
SS
2µA
where C
SS
is the capacitance on the TRACK/SS pin. Cur-
rent foldback and forced continuous mode are disabled
during the soft-start process.
Output voltage tracking can also be programmed externally
using the TRACK/SS pin. The output can be tracked up
and down with another regulator. Figure 4 and Figure 5
show an example waveform and schematic of ratiometric
tracking where the slave regulators output slew rate is
proportional to the master’s.
Figure 4. Output Ratiometric Tracking Waveform
Figure 5. Example Schematic of Ratiometric Output Voltage Tracking
TIME
SLAVE OUTPUT
MASTER OUTPUT
OUTPUT VOLTAGE
4623 F04
FREQCLKIN CLKOUT
V
IN
SV
IN
RUN
INTV
CC
MODE
TRACK/SS
PGOOD
V
OUT
FB
COMP
GND SGND
R
FB(MA)
40.2k
LTM4623
10µF
16V
V
IN
4V TO 15V
V
OUT(MA)
1.5V
3A
47µF
6.3V
C
SS
R
TR(BOT)
40.2k
R
FB(SL)
60.4k
R
TR(TOP)
60.4k
FREQ
V
IN
SV
IN
RUN
INTV
CC
MODE
TRACK/SS
PGOOD
V
OUT
FB
COMP
GND SGND
4623 F05
LTM4623
10µF
16V
V
OUT(SL)
1.2V
3A
47µF
6.3V
CLKIN CLKOUT
LTM4623
14
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Since the slave regulators TRACK/SS is connected to
the masters output through a R
TR(TOP)
/R
TR(BOT)
resistor
divider and its voltage used to regulate the slave output
voltage when TRACK/SS voltage is below 0.6V, the slave
output voltage and the master output voltage should satisfy
the following equation during start-up:
V
OUT(SL)
R
FB(SL)
R
FB(SL)
+ 60.4k
=
V
OUT(MA)
R
TR(BOT)
R
TR(TOP)
+R
TR(BOT)
The R
FB(SL)
is the feedback resistor and the R
TR(TOP)
/
R
TR(BOT)
is the resistor divider on the TRACK/SS pin of
the slave regulator, as shown in Figure 5.
Following the previous equation, the ratio of the master’s
output slew rate (MR) to the slaves output slew rate (SR)
is determined by:
MR
SR
=
R
FB(SL)
R
FB(SL)
+ 60.4k
R
TR(BOT)
R
TR(TOP)
+R
TR(BOT)
For example, V
OUT(MA)
=1.5V, MR = 1.5V/1ms and V
OUT(SL)
= 1.2V, SR = 1.2V/1ms. From the equation, we could solve
that R
TR(TOP)
= 60.4k and R
TR(BOT)
= 40.2k are a good
combination for the ratiometric tracking.
Figure 6. Output Coincident Tracking Waveform
The TRACK/SS pin will have the 2µA current source on
when a resistive divider is used to implement tracking
on the slave regulator. This will impose an offset on the
TRACK/SS pin input. Smaller value resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK/SS
pin offset to a negligible value.
The coincident output tracking can be recognized as a
special ratiometric output tracking in which the master’s
output slew rate (MR) is the same as the slaves output
slew rate (SR), waveform as shown in Figure 6.
From the equation, we could easily find that, in coincident
tracking, the slave regulators TRACK/SS pin resistor divider
is always the same as its feedback divider:
R
FB(SL)
R
FB(SL)
+ 60.4k
=
R
TR(BOT)
R
TR(TOP)
+R
TR(BOT)
For example, R
TR(TOP)
= 60.4k and R
TR(BOT)
= 60.4k is a
good combination for coincident tracking for a V
OUT(MA)
= 1.5V and V
OUT(SL)
= 1.2V application.
Power Good
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin is pulled
low when the output voltage exceeds a ±10% window
around the regulation point. To prevent unwanted PGOOD
glitches during transients or dynamic V
OUT
changes, the
LTM4623’s PGOOD falling edge includes a blanking delay
of approximately 52 switching cycles.
Stability Compensation
The LTM4623s internal compensation loop is designed and
optimized for use with low ESR ceramic output capacitors.
Table 7 is provided for most application requirements. In
case more phase margin is required for the application,
an additional 100pF feedforward capacitor (C
FF
) can be
placed between the V
OUT
and FB pins. The LTpowerCAD
design tool is available for control loop optimization.
TIME
MASTER OUTPUT
SLAVE OUTPUT
OUTPUT VOLTAGE
4623 F06
LTM4623
15
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RUN Enable
Pulling the RUN pin to ground forces the LTM4623 into
its shutdown state, turning off both power MOSFETs and
most of its internal control circuitry. Bringing the RUN pin
above 0.7V turns on the internal reference only, while still
keeping the power MOSFETs off. Increasing the RUN pin
voltage above 1.2V will turn on the entire chip.
Low Input Application
The LTM4623 module has a separate SV
IN
pin which makes
it suitable for low input voltage applications down to 2.375V.
The SV
IN
pin is the single input of the whole control circuitry
while the V
IN
pin is the power input which directly connects
to the drain of the top MOSFET. In most applications where
V
IN
is greater than 4V, connect SV
IN
directly to V
IN
with a
short trace. An optional filter, consisting of a resistor (
to 10Ω) between SV
IN
and V
IN
along with a 0.1µF bypass
capacitor between SV
IN
and ground, can be placed for
additional noise immunity. This filter is not necessary in
most cases if good PCB layout practices are followed (see
Figure 23). In a low input voltage application (2.375V to
4V), connect SV
IN
to an external voltage higher than 4V
with 1µF local bypass capacitor. See Operating Frequency
section. Figure 25 shows an example of a low input voltage
application. Please note the SV
IN
voltage cannot go below
the V
OUT
voltage.
Pre-Biased Output Start-Up
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging that
output pre-bias. The LTM4623 can safely power up into
a pre-biased output without discharging it.
The LTM4623 accomplishes this by forcing discontinuous
mode (DCM) operation until the TRACK/SS pin voltage
reaches 0.6V reference voltage. This will prevent the BG
from turning on during the pre-biased output start-up
which would discharge the output.
Please do not pre-bias LTM4623 with a voltage higher
than INTV
CC
(3.3V) voltage or a voltage higher than the
output voltage set by the feedback resistor (R
FB
).
Overtemperature Protection
The internal overtemperature protection monitors the
junction temperature of the module. If the junction
temperature reaches approximately 160°C, both power
switches will be turned off until the temperature drops
about 15°C cooler.
Radiated EMI Noise
High radiated EMI noise is a disadvantage for switching
regulators by nature. Fast switching turn-on and turn-off
make the large di/dt change in the converters, which act
as the radiation sources in most systems. LTM4623 in
-
tegrates the feature to minimize the radiated EMI noise to
meet the most applications with low noise requirements.
It is fully compliant with the E
N55022 Class B Standard.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param
-
eters defined by JESD
51-12 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients is
found in JESD 51-12 (Guidelines for Reporting and Using
Electronic Package Thermal Information).
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulators thermal performance in their ap
-
plication at various electrical and environmental operating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con
-
figuration section are, in and of themselves, not relevant to
providing guidance of thermal per
formance
; instead, the
derating curves provided in this data sheet can be used
in a manner that yields insight and guidance pertaining to
one’s application usage, and can be adapted to correlate
thermal performance to one’s own application.

LTM4623EY#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Ultrathin 20VIN, 3A Step-Down Module Regulator
Lifecycle:
New from this manufacturer.
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