LTM4623
16
4623fc
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applicaTions inForMaTion
The Pin Configuration section gives four thermal coeffi-
cients explicitly defined in JESD 51-12; these coefficients
are quoted or paraphrased next:
1.
θ
JA
, the thermal resistance from junction to ambient, is
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo
-
sure. This environment is sometimes referred to as
still air although natural convection causes the air to
move. This value is determined with the part mounted
to a 95mm × 76mm PCB with four layers.
2. θ
JCbottom
, the thermal resistance from junction to the
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the package. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the pack
-
age, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages, but the test
conditions don
t generally match the users application.
3. θ
JCtop
, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top of
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θ
JCbottom
, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4. θ
JB
, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resistance
where almost all of the heat flows through the bottom
of the µModule package and into the board, and is really
the sum of the θ
JCbottom
and the thermal resistance of
the bottom of the part through the solder joints and
through a portion of the board. The board temperature
is measured a specified distance from the package.
A graphical representation of the aforementioned ther
-
mal resistances is given in Figure 7; blue resistances are
contained within the μModule regulator
, whereas green
resistances are external to the µModule package.
As
a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a μModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot
-
tom of the µModule packageas the standard defines
for θ
JCtop
and θ
JCbottom
, respectively. In practice, power
loss is thermally dissipated in both directions away from
the packagegranted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4623 be aware there are multiple power
devices and components dissipating power, with a con
-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
Figure 7. Graphical Representation of JESD 51-12 Thermal Coefficients
4623 F07
µMODULE DEVICE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
CASE (TOP)-TO-AMBIENT
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
JUNCTION AMBIENT
CASE (BOTTOM)-TO-BOARD
RESISTANCE
LTM4623
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applicaTions inForMaTion
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicitybut
also, not ignoring practical realitiesan approach has been
taken using FEA software modeling along with laboratory
testing in a controlled environment chamber to reason
-
ably define and correlate the thermal resistance values
supplied in this data sheet
:
(1) Initially, FEA software is
used to accurately build the mechanical geometry of the
LTM4623 and the specified PCB with all of the correct
material coefficients along with accurate power loss source
definitions; (2) this model simulates a software-defined
JEDEC environment consistent with JESD 51-12 to predict
power loss heat flow and temperature readings at different
interfaces that enable the calculation of the JEDEC-defined
thermal resistance values; (3) the model and FEA software
is used to evaluate the LTM4623 with heat sink and airflow;
(4) having solved for and analyzed these thermal resistance
values and simulated various operating conditions in the
software model, a thorough laboratory evaluation replicates
the simulated conditions with thermocouples within a
controlled environment chamber while operating the device
at the same power loss as that which was simulated. An
outcome of this process and due diligence yields the set
of derating curves shown in this data sheet. After these
laboratory tests have been performed and correlated to
the LTM4623 model, then the θ
JB
and θ
BA
are summed
together to provide a value that should closely equal the
θ
JA
value because approximately 100% of power loss
flows from the junction through the board into ambient
with no airflow or top mounted heat sink.
The 1.0V, 1.5V, 3.3V and 5V loss curves in Figures8 to 11
can be used in coordination with the load current derating
curves in Figures 12 to 22 for calculating an approximate
θ
JA
thermal resistance for the LTM4623 with various air-
flow conditions. The power loss curves are taken at room
temperature, and are increased with a multiplicative factor
according to the ambient temperature. This approximate
factor is:
1.3 for 120°C at junction temperature. Maximum
load current is achievable while increasing ambient tem
-
perature as long as the junction temperature is less than
120
°C
, which is a 5°C guard band from maximum junction
temperature of 125°C. When the ambient temperature
reaches a point where the junction temperature is 120°C,
then the load current is lowered to maintain the junction at
120°C while increasing ambient temperature up to 120°C.
The derating curves are plotted with the output current
starting at 3A and the ambient temperature at 30°C. The
output voltages are 1.0V, 1.5V, 3.3V and 5V. These are
chosen to include the lower and higher output voltage
ranges for correlating the thermal resistance. Thermal
models are derived from several temperature measure
-
ments in a controlled temperature chamber along with
thermal modeling analysis. The junction temperatures are
monitored while ambient temperature is increased with
and without air
flow
. The power loss increase with ambient
temperature change is factored into the derating curves.
The junctions are maintained at 120°C maximum while
lowering output current or power with increasing ambient
temperature. The decreased output current will decrease the
internal module loss as ambient temperature is increased.
The monitored junction temperature of 120°C minus the
ambient operating temperature specifies how much module
temperature rise can be allowed. As an example, in Figure
16 the load current is derated to 2.5A at ~95°C with no air
flow or heat sink and the power loss for the 12V to 1.5V
at 2.5A output is about 1.0W. The 1.0W loss is calculated
with the ~0.8W room temperature loss from the 12V to
1.5V power loss curve at 2.5A in Figure 9, and the 1.3
multiplying factor at 120°C junction temperature. If the
95°C ambient temperature is subtracted from the 120°C
junction temperature, then the difference of 25°C divided
by 1.0W equals a 25°C/W θ
JA
thermal resistance. Table 4
specifies a 25°C/W value which is very close. Table 3 to
Table 6 provide equivalent thermal resistances for
1.0V to
5V outputs with and without airflow. The derived thermal
resistances in Table 3 to Table6 for the various condi
-
tions can be multiplied by the calculated power loss as
a function of ambient temperature to derive temperature
rise above ambient, thus maximum junction temperature.
Room temperature power loss can be derived from the ef
-
ficiency curves in the Typical Performance Characteristics
section and adjusted with the above ambient temperature
multiplicative factors. The printed cir
cuit board is a
1.6mm
thick 4-layer board with two ounce copper for the two outer
layers and one ounce copper for the two inner layers. The
PCB dimensions are 95mm × 76mm.
LTM4623
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Figure 8. 1.0V Output Power Loss Figure 9. 1.5V Output Power Loss Figure 10. 3.3V Output Power Loss
applicaTions inForMaTion
Figure 14. 16V to 1V Derating Curve,
No Heat Sink
Figure 12. 5V to 1V Derating Curve,
No Heat Sink
Figure 11. 5V Output Power Loss Figure 13. 12V to 1V Derating Curve,
No Heat Sink
Figure 15. 5V to 1.5V Derating Curve,
No Heat Sink
LOAD CURRENT (A)
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
4623 F08
1
2 3
POWER LOSS (W)
V
IN
= 16V
V
IN
= 12V
V
IN
= 5V
LOAD CURRENT (A)
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
4623 F09
1
2 3
POWER LOSS (W)
V
IN
= 16V
V
IN
= 12V
V
IN
= 5V
LOAD CURRENT (A)
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
4623 F10
1
2 3
POWER LOSS (W)
V
IN
= 16V
V
IN
= 12V
V
IN
= 5V
Figure 16. 12V to 1.5V Derating Curve,
No Heat Sink
LOAD CURRENT (A)
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
4623 F11
1
2 3
POWER LOSS (W)
V
IN
= 16V
V
IN
= 12V
AMBIENT TEMPERATURE (°C)
30
3.5
3
2.5
2
1.5
1
0.5
0
80 120
4623 F12
40 60
100 130
90
50 70
110
DERATED LOAD CURRENT (A)
0LFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
30
3.5
3
2.5
2
1.5
1
0.5
0
80 120
4623 F13
40 60
100 130
90
50 70
110
DERATED LOAD CURRENT (A)
0LFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
30
3.5
3
2.5
2
1.5
1
0.5
0
80 120
4623 F14
40 60
100 130
90
50 70
110
DERATED LOAD CURRENT (A)
0LFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
30
3.5
3
2.5
2
1.5
1
0.5
0
80 120
4623 F15
40 60
100 130
90
50 70
110
DERATED LOAD CURRENT (A)
0LFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
30
3.5
3
2.5
2
1.5
1
0.5
0
80 120
4623 F16
40 60
100 130
90
50 70
110
DERATED LOAD CURRENT (A)
0LFM
200LFM
400LFM

LTM4623EY#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Ultrathin 20VIN, 3A Step-Down Module Regulator
Lifecycle:
New from this manufacturer.
Delivery:
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