REV. 0
AD9752
–15–
AD9752
IOUTA
IOUTB
C
OPT
200V
U1
V
OUT
= I
OUTFS
3 R
FB
I
OUTFS
= 10mA
R
FB
200V
Figure 32. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS, POWER
SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these circuits, the imple-
mentation and construction of the printed circuit board design
is as important as the circuit design. Proper RF techniques must
be used for device selection, placement and routing as well as
power supply bypassing and grounding to ensure optimum
performance. Figures 42-47 illustrate the recommended printed
circuit board ground, power and signal plane layouts which are
implemented on the AD9752 evaluation board.
One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution
(i.e., AVDD, DVDD). This is referred to as Power Supply
Rejection Ratio (PSRR). For dc variations of the power supply,
the resulting performance of the DAC directly corresponds to a
gain error associated with the DAC’s full-scale current, I
OUTFS
.
AC noise on the dc supplies is common in applications where
the power distribution is generated by a switching power supply.
Typically, switching power supply noise will occur over the
spectrum from tens of kHz to several MHz. PSRR vs. frequency
of the AD9752 AVDD supply, over this frequency range, is
given in Figure 33.
FREQUENCY – MHz
90
80
60
1.00.26
PSRR – dB
0.5 0.75
70
Figure 33. Power Supply Rejection Ratio of AD9752
Note that the units in Figure 33 are given in units of (amps out)/
(volts in). Noise on the analog power supply has the effect of
modulating the internal switches, and therefore the output
current. The voltage noise on the dc power, therefore, will be
added in a nonlinear manner to the desired I
OUT
. Due to the
relative different sizes of these switches, PSRR is very code depen-
dent. This can produce a mixing effect which can modulate low
frequency power supply noise to higher frequencies. Worst case
PSRR for either one of the differential DAC outputs will occur
when the full-scale current is directed towards that output. As a
result, the PSRR measurement in Figure 33 represents a worst
case condition in which the digital inputs remain static and the
full scale output current of 20 mA is directed to the DAC out-
put being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV rms of noise and for
simplicity sake (i.e., ignore harmonics), all of this noise is con-
centrated at 250 kHz. To calculate how much of this undesired
noise will appear as current noise super imposed on the DAC’s
full-scale current, I
OUTFS
, one must determine the PSRR in dB
using Figure 33 at 250 kHz. To calculate the PSRR for a given
R
LOAD
, such that the units of PSRR are converted from A/V to
V/V, adjust the curve in Figure 33 by the scaling factor 20 × Log
(R
LOAD
). For instance, if R
LOAD
is 50 Ω, the PSRR is reduced
by 34 dB (i.e., PSRR of the DAC at 1 MHz which is 74 dB in
Figure 33 becomes 40 dB V
OUT
/V
IN
).
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9752 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a
system. In general, AVDD, the analog supply, should be de-
coupled to ACOM, the analog common, as close to the chip as
physically possible. Similarly, DVDD, the digital supply, should
be decoupled to DCOM as close as physically as possible.
For those applications that require a single +5 V or +3 V supply
for both the analog and digital supply, a clean analog supply
may be generated using the circuit shown in Figure 34. The
circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained using low
ESR type electrolytic and tantalum capacitors.
100mF
ELECT.
10-22mF
TANT.
0.1mF
CER.
TTL/CMOS
LOGIC
CIRCUITS
+5V OR +3V
POWER SUPPLY
FERRITE
BEADS
AVDD
ACOM
Figure 34. Differential LC Filter for Single +5 V or +3 V
Applications
Maintaining low noise on power supplies and ground is critical
to obtaining optimum results from the AD9752. If properly
implemented, ground planes can perform a host of functions on
high speed circuit boards: bypassing, shielding, current trans-
port, etc. In mixed signal design, the analog and digital portions
of the board should be distinct from each other, with the analog
ground plane confined to the areas covering the analog signal
traces, and the digital ground plane confined to areas covering
the digital interconnects.
All analog ground pins of the DAC, reference and other analog
components should be tied directly to the analog ground plane.
The two ground planes should be connected by a path 1/8
to 1/4 inch wide underneath or within 1/2 inch of the DAC to
