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AD9752
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DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per °C. For reference drift, the drift is reported
in ppm per °C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range for an output containing mul-
tiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the
peak spurious signal in the region of a removed tone.
+1.20V REF
AVDD ACOM
REFLO
ICOMP
PMOS
CURRENT SOURCE
ARRAY
+5V
SEGMENTED SWITCHES
FOR DB11–DB3
LSB
SWITCHES
REFIO
FS ADJ
DVDD
DCOM
CLOCK
+5V
R
SET
2kV
0.1mF
DVDD
DCOM
IOUTA
IOUTB
0.1mF
AD9752
SLEEP
50V
RETIMED
CLOCK
OUTPUT*
LATCHES
DIGITAL
DATA
TEKTRONIX
AWG-2021
W/OPTION 4
LECROY 9210
PULSE GENERATOR
CLOCK
OUTPUT
50V
20pF
50V
20pF
100V
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50V INPUT
MINI-CIRCUITS
T1-1T
* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
150pF
Figure 2. Basic AC Characterization Test Setup
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AD9752
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Typical AC Characterization Curves @ +5 V Supplies
(AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, 50 Doubly Terminated Load, Differential Output, T
A
= +25C, SFDR up to Nyquist, unless otherwise noted)
f
OUT
– MHz
SFDR – dB
90
80
40
0
1 100
10
70
60
50
25MSPS
50MSPS
125MSPS
65MSPS
Figure 3. SFDR vs. f
OUT
@ 0 dBFS
f
OUT
– MHz
SFDR – dBc
90
80
40
0
530
20
70
60
50
10 15 25
–12dBFS
–6dBFS
0dBFS
Figure 6. SFDR vs. f
OUT
@ 65 MSPS
A
OUT
– dBFS
SFDR – dB
90
70
–30 –25
0
–10
80
–20 –15 –5
40
60
50
2.27MHz@25MSPS
4.55MHz@50MSPS
5.91MHz@65MSPS
11.36MHz@125MSPS
Figure 9. Single-Tone SFDR vs. A
OUT
@ f
OUT
= f
CLOCK
/11
SFDR – dB
90
80
40
0
214
12
70
60
50
46810
–12dBFS
0dBFS
–6dBFS
f
OUT
– MHz
Figure 4. SFDR vs. f
OUT
@ 25 MSPS
SFDR – dB
90
80
40
0
10 60
40
70
60
50
20 30 50
–6dBFS
0dBFS
–12dBFS
f
OUT
– MHz
Figure 7. SFDR vs. f
OUT
@ 125 MSPS
A
OUT
– dBFS
SFDR – dB
90
70
–30 –25
0
–10
80
–20 –15 –5
40
60
50
5MHz@25MSPS
10MHz@50MSPS
13MHz@65MSPS
25MHz@125MSPS
Figure 10. Single-Tone SFDR vs.
A
OUT
@ f
OUT
= f
CLOCK
/5
f
OUT
– MHz
SFDR – dBc
90
80
40
05 25
10
70
60
50
15 20
–12dBFS
–6dBFS
0dBFS
Figure 5. SFDR vs. f
OUT
@ 50 MSPS
f
OUT
– MHz
SFDR – dBc
90
0
212
8
80
70
46 10
50
60
10mA FS
20mA FS
5mA FS
Figure 8. SFDR vs. f
OUT
and I
OUTFS
@ 25 MSPS and 0 dBFS
f
CLOCK
– MSPS
SNR – dB
0
20 120
80
80
40 60 100
60
70
50
20mA FS
10mA FS
5mA FS
Figure 11. SNR vs. f
CLOCK
and I
OUTFS
@ f
OUT
= 2 MHz and 0 dBFS
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AD9752
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CODE
ERROR – LSB
0
4000
1000 2000 3000
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
Figure 12. Typical INL
f
OUT
– MHz
SIGNAL AMPLITUDE – dBm
0
60
10 20 30
0
–10
–20
–30
–40
–100
–50
–60
–70
–80
–90
40 50
f
CLK
= 125MSPS
f
OUT1
= 13.5MHz
f
OUT2
= 14.5MHz
A
OUT
= 0dBFS
SFDR = 68.4dBc
Figure 15. Dual-Tone SFDR
CODE
ERROR – LSB
0
4000
1000 2000 3000
0.1
0.0
–0.1
–0.2
–0.3
–0.5
–0.4
Figure 13. Typical DNL
SIGNAL AMPLITUDE – dBm
0
30.0
5.0 10.0 15.0
0
–10
–20
–30
–40
–100
–50
–60
–70
–80
–90
20.0 25.0
f
CLK
= 65MSPS
f
OUT1
= 6.25MHz
f
OUT2
= 6.75MHz
f
OUT3
= 7.25MHz
f
OUT4
= 7.75MHz
SFDR = 69dBc
AMPLITUDE = 0dBFS
f
OUT
– MHz
Figure 16. Four-Tone SFDR
TEMPERATURE – 8C
SFDR – dBc
–55 95–30 –5 20
90
70
80
50
60
45 70
f
OUT
= 4MHz
f
OUT
= 10MHz
f
OUT
= 29MHz
f
OUT
= 40MHz
Figure 14. SFDR vs. Temperature @
125 MSPS, 0 dBFS

AD9752ARZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 12-Bit 100 MSPS
Lifecycle:
New from this manufacturer.
Delivery:
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