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9VRS4818BKLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
DATASHEET
FUSION II CLOCK GENERATOR
9VRS4818B
IDT®
FUSION II CLOCK GENERATOR 1
9VRS4818B REV A 062512
General Description
The 9VRS4818B is a 1.5V Core main clock synthesizer
chip for AMD Fusion platform. An SMBus interface allows
full control of the device.
Recommended Application
Very Low Power Clock Generator for AMD Fusion II
Platforms
Input/Output Features
• Low power differential outputs with integrated series
resistors for Zo=50ohm systems
• 12 - Differential PCIe Gen2 SRC pairs w/dedicated
CLKREQ# pins
• 3 - Differential PCIe Gen2 SATA_DISPLAY pairs
w/microspread capability
• 2 - 48MHz USB clocks (180 degrees out of phase for EMI
reduction)
• 2 - 14.318MHz REF clock outputs
• 1 - 25MHz LAN clock output that can run from VDD
suspend rail
• 1 - CkPwrGd/WOL_STOP#
• 1 - VDD_SUSPEND pin
• 1- RESET_IN# pin
Features/Benefits
• 1.5V Core for minimal Power consumption
• Spread Spectrum for EMI reduction
• Outputs may be disabled via SMBus
• External crystal load capacitors for maximum frequency
accuracy
Key Specifications
• SRC/SATA_DISP output cycle-to-cycle jitter < 125ps
• 14.318MHz output cycle-to-cycle jitter < 200ps
• 48MHz output cycle-to-cycle jitter < 130ps
• SRC/SATA_DISP output phase jitter < 3.1ps rms (PCIe
Gen2)
• +/- 100ppm frequency accuracy on all clocks, (assuming
REF is trimmed to 0 ppm)
• 31.5KHz spread modulation frequency; passes USB3.0
compliance test
Pin Configuration
48MHz_0
VDD48_3.3
^RESET_IN#
^CLKREQ4#
^CLKREQ5#
^CLKREQ6#
VDDREF_3.3
REF1
REF0
GNDREF
^CLKREQ7#
^CLKREQ8#
^CLKREQ9#
SMBCLK
SMBDAT
25MHz
GND25M
VDD25_SUSP3.3
72 71 70 69 68 67 66 65 6 4 63 62 61 60 59 58 57 56 55
48MHz_1
1 54
X1_25
GND48 2 53
X2_25
^CLKREQ3# 3 52
^CKPwrGd/WOL_STOP#
^CLKREQ2# 4 51 ^CLKREQ10#
^CLKREQ1#
5 50
^CL KREQ11#
^CLKREQ0#
6
49 VDD SATADISP_1.5
SRC0T_LPRS
7
48 GNDSATADISP
SRC0C_LPRS
8
47 SATA_DISP0C_LPRS
SRC1T_LPRS
9
46 SATA_DISP0T_LPRS
SRC1C_LPRS 10 45 SATA_DISP1C_LPRS
GNDSRC 11 44 SATA_DISP1T_LPRS
VDDSRC_LIO 12 43 GNDSATADISP
SRC2T_L PRS 13 42 VDD SATADISP_LI O
SRC2C_LPRS 14 41 SATA_DISP2C_LPRS
SRC3T_LPRS 15 40 SATA_DISP2T_LPRS
SRC3C_LPRS 16 39 GNDSRC
VDDSRC_1.5 17 38 SRC11C_LPRS
GNDSRC 18 37 SRC 11T_LPRS
19 20 21 22 23 24 25 26 2 7 28 29 30 31 32 33 34 35 36
SRC4T_LPRS
SRC4C_LPRS
SRC5T_LPRS
SRC5C_LPRS
SRC6T_LPRS
SRC6C_LPRS
SRC7T_LPRS
SRC7C_LPRS
GNDSRC
VDDSRC_LIO
SRC8T_LPRS
SRC8C_LPRS
SRC 9T_LPRS
SRC9C_LPRS
VDDSRC_1.5
GNDSRC
SRC10T_LPRS
SRC10C_LPRS
^ Indicates that pin has 100Kohm internal pullup resistor.
9VRS4818
9VRS4818B
FUSION II CLOCK GENERATOR
IDT®
FUSION II CLOCK GENERATOR 2
9VRS4818B REV A 062512
Pin Descriptions
PIN # PIN NAME PIN TYPE DESCRIPTION
1 48MHz_1 OUT 48MHz clock output. (180 degrees out of phase with 48MHz_0)
2 GND48 GND Ground pin for the 48MHz outputs
3^CLKREQ3# IN
Output enable for SRC/PCI Express output pair '3'
0 = enabled, 1 = Low/Low. This pin has a 120K internal pull up resistor.
4^CLKREQ2# IN
Output enable for SRC/PCI Express output pair '2'
0 = enabled, 1 = Low/Low. This pin has a 120K internal pull up resistor.
5^CLKREQ1# IN
Output enable for SRC/PCI Express output pair '1'
0 = enabled, 1 = Low/Low. This pin has a 120K internal pull up resistor.
6^CLKREQ0# IN
Output enable for SRC/PCI Express output pair '0'
0 = enabled, 1 = Low/Low. This pin has a 120K internal pull up resistor.
7 SRC0T_LPRS OUT
True clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series resistor
needed)
8 SRC0C_LPRS OUT
Complement clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series
resistor needed)
9 SRC1T_LPRS OUT
True clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series resistor
needed)
10 SRC1C_LPRS OUT
Complement clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series
resistor needed)
11 GNDSRC GND Ground
p
in for the SRC out
p
ut
s
12 VDDSRC_LIO PWR Su
pp
l
y
for SRC out
p
uts, 1.05V to 1.5V nominal
13 SRC2T_LPRS OUT
True clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series resistor
needed
)
14 SRC2C_LPRS OUT
Complement clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series
resistor needed
)
15 SRC3T_LPRS OUT
True clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series resistor
needed
)
16 SRC3C_LPRS OUT
Complement clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series
resistor needed
)
17
VDDSRC_1.5
PWR Su
pp
l
y
for SRC core and out
p
uts, 1.5V nominal
18
GNDSRC
GND Ground
p
in for the SRC out
p
ut
s
19 SRC4T_LPRS OUT
True clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series resistor
needed
)
20 SRC4C_LPRS OUT
Complement clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series
resistor needed
)
21 SRC5T_LPRS OUT
True clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series resistor
needed
)
22 SRC5C_LPRS OUT
Complement clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series
resistor needed
)
23 SRC6T_LPRS OUT
True clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series resistor
needed
)
24 SRC6C_LPRS OUT
Complement clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series
resistor needed
)
25 SRC7T_LPRS OUT
True clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series resistor
needed)
26 SRC7C_LPRS OUT
Complement clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series
resistor needed)
27 GNDSRC GND Ground pin for the SRC outputs
28 VDDSRC_LIO PWR Supply for SRC outputs, 1.05V to 1.5V nominal
29
SRC8T_LPRS OUT
True clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series resistor
needed)
30 SRC8C_LPRS OUT
Complement clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series
resistor needed)
31 SRC9T_LPRS OUT
True clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series resistor
needed)
32 SRC9C_LPRS OUT
Complement clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series
resistor needed)
33 VDDSRC_1.5 PWR Su
pp
l
y
for SRC core and out
p
uts, 1.5V nominal
34 GNDSRC GND Ground
p
in for the SRC out
p
ut
s
35 SRC10T_LPRS OUT
True clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series resistor
needed
)
36 SRC10C_LPRS OUT
Complement clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series
resistor needed
)
9VRS4818B
FUSION II CLOCK GENERATOR
IDT®
FUSION II CLOCK GENERATOR 3
9VRS4818B REV A 062512
Pin Descriptions (cont.)
PIN # PIN TYPE DESCRIPTION
37 SRC11T_LPRS OUT
True clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series resistor
needed
)
38 SRC11C_LPRS OUT
Complement clock of low power differential SRC clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series
resistor needed)
39 GNDSRC GND Ground pin for the SRC outputs
40 SATA_DISP2T_LPRS OUT
True clock of low power differential SATA_DISPlay clock pair. (no 50 ohm shunt re sistor to GND and no 33 ohm
series resistor needed)
41 SATA_DISP2C_LPRS OUT
Complement clock of low pow er differential SATA_DISPlay clock pair. (no 50 ohm shunt resistor to GND and no 33
ohm series resistor needed)
42 VDDSATADISP_LIO PWR Supply for SATA_DISPlay outputs, 1.05V to 1.5V nominal
43 GNDSATADISP GND Ground pin for the SATA_DISPlay outputs
44 SATA_DISP1T_LPRS OUT
True clock of low power differential SATA_DISPlay clock pair. (no 50 ohm shunt re sistor to GND and no 33 ohm
series resistor needed)
45 SATA_DISP1C_LPRS OUT
Complement clock of low pow er differential SATA_DISPlay clock pair. (no 50 ohm shunt resistor to GND and no 33
ohm series resistor needed)
46 SATA_DISP0T_LPRS OUT
True clock of low power differential SATA_DISPlay clock pair. (no 50 ohm shunt re sistor to GND and no 33 ohm
series resistor needed)
47 SATA_DISP0C_LPRS OUT
Complement clock of low pow er differential SATA_DISPlay clock pair. (no 50 ohm shunt resistor to GND and no 33
ohm series resistor needed
48 GNDSATADISP GND Ground
p
in for the SATA_DISPla
y
out
p
uts
49 VDDSATADISP_1.5 PWR Su
pp
l
y
for SATA_DISPla
y
core and out
p
uts, 1.5V nominal
50 ^CLKREQ11# IN
Output enable for SRC/PCI Express output pair '11'
0 = enabled, 1 = Low/Low. This
p
in has a 120K internal
p
ull u
p
resistor.
51 ^CLKREQ10# IN
Output enable for SRC/PCI Express output pair '10'
0 = enabled, 1 = Low/Low. This
p
in has a 120K internal
p
ull u
p
resistor.
52 ^CKPwrGd/WOL_STOP# IN
This devices powers up the clock chip and latched strap pins when asserted high. When asserted low, the clock is
powered down except for the 25M output, if VDD25_SUSP3.3 is maintained.
0 = Power Dow n, 1 = normal o
p
eration.
53
X2_25
OUT Cr
y
st al o ut
p
ut, nominall
y
25MHz
54
X1_25
IN Cr
y
st al i n
p
ut, nominall
y
25MHz
55 VDD25_ SUSP3.3 PWR
Power pin for the 25 M output and XTAL oscillator. This pin allows the 25MHz outp ut when the rest of the power is
colla
p
sed and VttPwrGd/WOL_STOP# is low.
56 GND25M GND Ground pin for the 25MHz output and XTAL oscillator circuit
57 25MHz OUT 25MHz clock output.
58 SMBDAT I/O Data pin for SMBus circuitry, 5V tolerant.
59 SMBCLK IN Clock pin of SMBus circuitry, 5 V tolerant.
60 ^C LKREQ9# IN
Output enable for SRC/PCI Express output pair '9'
0 = enabled, 1 = Low/Low. This
p
in has a 120K internal
p
ull u
p
resistor.
61 ^C LKREQ8# IN
Output enable for SRC/PCI Express output pair '8'
0 = enabled, 1 = Low/Low. This
p
in has a 120K internal
p
ull u
p
resistor.
62 ^C LKREQ7# IN
Output enable for SRC/PCI Express output pair '7'
0 = enabled, 1 = Low/Low. This
p
in has a 120K internal
p
ull u
p
resistor.
63 GNDREF GND Ground pin for the REF outputs.
64 REF0 OUT 14.318 MHz reference clock, 3.3V
65 REF1 OUT 14.318 MHz reference clock, 3.3V
66 VDDREF_3.3 PWR Ref, XTAL power supply, nominal 3.3V
67 ^C LKREQ6# IN
Output enable for SRC/PCI Express output pair '6'
0 = enabled, 1 = Low/Low. This pin has a 120K internal pull up resistor.
68 ^C LKREQ5# IN
Output enable for SRC/PCI Express output pair '5'
0 = enabled, 1 = Low/Low. This pin has a 120K internal pull up resistor.
69 ^C LKREQ4# IN
Output enable for SRC/PCI Express output pair '4'
0 = enabled, 1 = Low/Low. This pin has a 120K internal pull up resistor.
70 ^R ESET_IN#
OD
I/O
As an input it resets the device to the power up default state. As an output, it is driven low when the internal watchdog
hardware timer expires. It is cleared when the internal watchdog hardware timer is reset or disabled. The input is falling
edge triggered.
0 = Restore Settin
g
s, 1 = normal o
p
erat ion.
71 VDD48_3.3 PWR Power
p
in for the 48MHz and SIO out
p
uts and core. 3.3
V
72 48MHz_0 OUT 48MHz clock out
p
ut.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

9VRS4818BKLFT

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Buy 9VRS4818BKLFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products AMD FUSION CLOCK
Lifecycle:
New from this manufacturer.
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