9VRS4818B
FUSION II CLOCK GENERATOR
IDT®
FUSION II CLOCK GENERATOR 16
9VRS4818B REV A 062512
Byte SMBUS Table: SRC PLL NDiv0 Output Divider and Single Ended Output Slew Rate Control Register
20 Name Control Function Type 0 1 Default
Bit 7
SRC NDiv0 LSB N Divider Programming RW X
Bit 6
0
Bit 5
0
Bit 4
1
Bit 3
1
Bit 2
0
Bit 1
1
Bit 0
1
Byte SMBUS Table: SATA_DISP PLL NDiv0 and SATA_ DISP Output Divider Re gister
21 Name Control Function Type 0 1 Default
Bit 7
SATA_DISP NDiv0 LSB N Divider Programming RW X
Bit 6
0
Bit 5
0
Bit 4
1
Bit 3
1
Bit 2
SATA_DISPDiv2 RW 000 = /2 001 = /3 0
Bit 1
SATA_DISPDiv1 RW 010= /4 011 = /5 1
Bit 0
SATA_DISPDiv0 RW 100 = /7 101 - 111 = /1 1
Reserved
Reserved
Reserved
N Divider LSB (bit 0) for SRC M/N programming.
Reserved
Reserved
Reserved
Reserved
Bytes 22 to 63 Are Reserved
SATA_DISP D ivide r Ratio
Programming Bits
Reserved
N Divider LSB (bit 0) for SATA_DISP M/N programming.
Reserved
Reserved
Reserved
Clock Periods Differential Outputs with Spread Spectrum Enabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
Lg- -SSC -ppm error 0ppm + ppm error +SSC Lg+
Absolute
Period
Short-term
Average
Long -Term
Average
Period
Long-Term
Average
Short-term
Average
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Nominal Maximum Maximum Maximum
Signal Name SRC
9.87400 9.99900 9.99900 10.00000 10.00100 10.05130 10.17630 ns 1,2
Clock Periods Differential Outputs with Spread Spectrum Disabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
Lg- -SSC -ppm error 0ppm + ppm error +SSC Lg+
Absolute
Period
Short-term
Average
Long -Term
Average
Period
Long-Term
Average
Short-term
Average
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Nominal Maximum Maximum Maximum
Signal Name
SRC/SATA_DISP
9.87400 9.99900 10.00000 10.00100 10.17630 ns 1,2
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
2
All Lon
g
Term Accurac
y
and Clock Period s
p
ecifications are
g
uaranteed assumin
g
that 25MHz out
p
ut is at 25MHz
Notes
Symbol
Defini tion
Notes
Symbol
Defini tion
Units
Measurement Window
Measurement Window
Units
9VRS4818B
FUSION II CLOCK GENERATOR
IDT®
FUSION II CLOCK GENERATOR 17
9VRS4818B REV A 062512
Power-up Sequence Requirement
Marking Diagram
Notes:
1. “LOT” is the lot code.
2. “COO” denotes country of origin.
3. YYWW is the last two digits of the year and week that the part was assembled.
4. “LF” designates RoHS compliant package.
ICS
9VRS4818BKLF
LOT
COO YYWWP
9VRS4818B
FUSION II CLOCK GENERATOR
IDT®
FUSION II CLOCK GENERATOR 18
9VRS4818B REV A 062512
Package Outline and Package Dimensions (72-pin MLF)
Ordering Information
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“B” is the device revision designator (will not correlate with the datasheet revision).
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
Part / Order Number Shipping Packaging Package Temperature
9VRS4818BKLF Trays 72-pin MLF 0 to +70° C
9VRS4818BKLF8 Tape and Reel 72-pin MLF 0 to +70° C
Millimeters
Symbol Min Max
A0.81.0
A1 0 0.05
A3 0.25 Reference
b 0.18 0.3
e 0.50 BASIC
D x E BASIC 10.00 x 10.00
D2 MIN./MAX. 5.75 6.15
E2 MIN./MAX. 5.75 6.15
L MIN./MAX. 0.3 0.5
N
D
18
N
E
18
Anvil
Singulation
-- or --
Sawn
Singulation
1
2
N
E
D
Index Area
Top View
Seating Plane
A3
A1
C
A
L
E2
E2
2
D2
D2
2
e
C0.08
(Ref)
N
D
& N
E
Odd
(Ref)
N
D
& N
E
Even
(N
D
-1)x
(Ref)
e
N
1
2
b
Thermal Base
(Typ)
If N
D
& N
E
are Even
(N
E
-1)x
(Ref)
e
e
2

9VRS4818BKLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products AMD FUSION CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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