9VRS4818BKLFT Datasheet 9VRS4818BKLFT, 9VRS4818BKLF | P10-P12

9VRS4818B

FUSION II CLOCK GENERATOR

IDT®

FUSION II CLOCK GENERATOR 10

9VRS4818B REV A 062512

Electrical Characteristics–REF-14.318MHz

Electrical Characteristics–25MHz

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes

Long Accuracy ppm

see Tperiod min-max

values

-50 0 50 ppm 1,2

Long Term Jitter t

@ 10us 200 500 ps 1,2,3

Clock period T

PERIOD

14.318MHz output nominal 69.8413 ns 2

Clock Low Time T

LOW

Measure from V

= 50% 2 33 ns 2

Clock High Time T

HIGH

Measure from V

= 50% 2 34 ns 2

Output High Voltage V

= -1 mA 2.4 2.8 3.3 V 1

Out

ut Low Volta

= 1 mA

00.4V1

Rise Time t

= 20% of V

= 80%of V

1.2 1.5 ns 1

Fall Time t

= 20% of V

= 80%of V

1.2 1.5 ns 1

Skew t

SKEW

Measure from V

= 50% 71 250 ps 1

Duty Cycle d

= V

/2 45 50 55 % 1

Jitter, Cycle to Cycle t

CYC-CYC

Measure from V

= 50% 125 200 ps 1,3

Jitter, Peak to Peak t

jPK-PK

Measure from V

= 50%

(0.9V)

jpk-pk

=[|t

jcyc-cyc

max| + |t

jcyc-

min|]/2

100 200 ps 1,3

*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%

Guaranteed by design and characterization, not 100% tested in production.

All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz output is at 25MHz

IDT recommended and/or chipset vendor layout guidelines must be followed to meet this specification

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes

Long Accuracy ppm

see Tperiod min-max

values

-50 0 50 ppm 1,2

Long Term Jitter t

@ 10us 200 250 ps 1,2,3

Clock period T

PERIOD

25MHz XTAL output

nominal

40.0000 ns 2

Clock Low Time T

LOW

Measure from V

= 50% 2 16.6 ns 2

Clock High Time T

HIGH

Measure from V

= 50% 2 17.2 ns 2

Output High Voltage V

= -1 mA 2.4 2.8 3.3 V 1

Out

ut Low Volta

= 1 mA

00.4V1

Rise Time t

= 10% of V

= 90%of V

2.4 3 ns 1

Fall Time t

= 10% of V

= 90%of V

2.4 3 ns 1

Duty Cycle d

= 50% 45 48 55 % 1

Jitter, Cycle to Cycle t

CYC-CYC

Measure from V

= 50% 180 200 ps 1,3

Jitter, Peak to Peak t

jPK-PK

Measure from V

= 50%

jpk-pk

=[|t

jcyc-cyc

max| + |t

jcyc-

min|]/2

160 200 ps 1,3

*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%

Guaranteed by design and characterization, not 100% tested in production.

All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz output is at 25MHz

IDT recommended and/or chipset vendor layout guidelines must be followed to meet this specification

9VRS4818B

FUSION II CLOCK GENERATOR

IDT®

FUSION II CLOCK GENERATOR 11

9VRS4818B REV A 062512

General SMBus Serial Interface Information for 9VRS4818B

How to Write

• Controller (host) sends a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) sends the byte count = X

• IDT clock will acknowledge

• Controller (host) starts sending Byte N through Byte

N+X-1

• IDT clock will acknowledge each byte one at a time

• Controller (host) sends a Stop bit

How to Read

• Controller (host) will send a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) will send a separate start bit

• Controller (host) sends the read address

• IDT clock will acknowledge

• IDT clock will send the data byte count = X

• IDT clock sends Byte N+X-1

• IDT clock sends Byte 0 through Byte X (if X

(H)

was

written to Byte 8)

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Write Operation

Controller (Host) IDT (Slave/Receiver)

TstarT bit

Slave Address

WR WRite

ACK

Beginning Byte = N

ACK

Data Byte Count = X

ACK

Beginning Byte N

X Byte

ACK

O O

Byte N + X - 1

ACK

PstoP bit

Read Address Write Address

(H)

Index Block Read Operation

Controller (Host) IDT (Slave/Receiver)

TstarT bit

Slave Address

WR WRite

ACK

Beginning Byte = N

ACK

RT Repeat starT

Slave Address

RD ReaD

ACK

Data Byte Count=X

ACK

X Byte

Beginning Byte N

ACK

O O

Byte N + X - 1

N Not acknowledge

PstoP bit

9VRS4818B

FUSION II CLOCK GENERATOR

IDT®

FUSION II CLOCK GENERATOR 12

9VRS4818B REV A 062512

Byte SMBus Table: Output Enable Control Register

0 Name Description Type 0 1 Default

Bit 7

25M_OE Output Enable RW Low Enabled 1

Bit 6

REF1_OE Outp ut Enable RW Low Enabled 1

Bit 5

REF0_OE Outp ut Enable RW Low Enabled 1

Bit 4

SATA_DISP2_OE Output Enable RW Low/Low Enabled 1

Bit 3

SATA_DISP1_ OE Out

ut Enable RW Low/Low Enabled 1

Bit 2

SATA_DISP0_ OE Out

ut Enable RW Low/Low Enabled 1

Bit 1

48MHz_1_OE Out

ut Enable RW Low Enabled 1

Bit 0

48MHz_0_OE Output Enable RW Low Enabled 1

Byte SMBus Table:CKLREQ and Output Control Register

1 Name Control Function Type 0 1 Default

Bit 7

CLKREQ7 CLKREQ 7controls SRC7 RW Does not control Controls 0

Bit 6

CLKREQ6 CLKREQ6 controls SRC6 RW Does not control Controls 0

Bit 5

CLKREQ5 CLKREQ5 controls SRC5 RW Does not control Controls 0

Bit 4

CLKREQ4 CLKREQ4 controls SRC4 RW Does not control Controls 0

Bit 3

SRC11_OE Output Enable RW Low/Low Enabled 1

Bit 2

SRC10_OE Output Enable RW Low/Low Enabled 1

Bit 1

SRC9 _OE Output Enable RW Low/Low Enabled 1

Bit 0

SRC8 _OE Output Enable RW Low/Low Enabled 1

Byte SMBus Table: Output Enable Control Register

2 Name Control Function Type 0 1 Default

Bit 7

SRC7 _OE Output Enable RW Low/Low Enabled 1

Bit 6

SRC6 _OE Output Enable RW Low/Low Enabled 1

Bit 5

SRC5 _OE Output Enable RW Low/Low Enabled 1

Bit 4

SRC4 _OE Output Enable RW Low/Low Enabled 1

Bit 3

SRC3 _OE Output Enable RW Low/Low Enabled 1

Bit 2

SRC2 _OE Output Enable RW Low/Low Enabled 1

Bit 1

SRC1 _OE Output Enable RW Low/Low Enabled 1

Bit 0

SRC0 _OE Output Enable RW Low/Low Enabled 1

Byte SMBus Table: SATA_DISP/HTT Frequency and Output Enable Control Registe

3 Name Control Function Type 0 1 Default

Bit 7

CLKREQ3 CLKREQ3 controls SRC3 RW Does not control Controls 0

Bit 6

CLKREQ2 CLKREQ2 controls SRC2 RW Does not control Controls 0

Bit 5

WOL_EN

Enables 25M output in Suspend

St ate

25M does not run whe n

VDD_SUSP is present and

WOL_STOP# = 0

25M does RUNS when

VDD_SUSP is present and

WOL_STOP# = 0

Bit 4

SATA_DISP_FS4 SATA_DISP Freq. Select MSB RW 0

Bit 3

SATA_DISP_FS3 SATA_D ISP Freq. S ele ct RW 1

Bit 2

SATA_DISP_FS2 SATA_D ISP Freq. S ele ct RW 1

Bit 1

SATA_DISP_FS1 SATA_DISP Freq. Select RW 1

Bit 0

SATA_DISP_FS0 SATA_DISP Freq. Select LSB RW 1

Byte SMBus Table: SRC Frequency Control Register

4 Name Control Function Type 0 1 Default

Bit 7

CLKREQ1 CLKREQ1 controls SRC1 RW Does not control Controls 0

Bit 6

CLKREQ0 CLKREQ0 controls SRC0 RW Does not control Controls 0

Bit 5

Bit 4

SRC SS TYPE Down or Cen ter S

read RW Down Center 0

Bit 3

SRC_SS_RNG Normal or Low Range RW

Normal Low Ran

(

<0.25%

)

Bit 2

SRC_SS_EN

SRC S

read Enable

RW Off

Bit 1

SRC_ SS_SEL1

SRC S

read Amount RW 0

Bit 0

SRC_SS_SEL0 SRC Spread Amount RW 0

Reserved

See SRC Spread Select Table

Def ault Corresponds to 100MHz.

See SATA_DISP Frequency Select Table

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

9VRS4818BKLFT

Mfr. #:

Buy 9VRS4818BKLFT

Manufacturer:

IDT

Description:

Clock Generators & Support Products AMD FUSION CLOCK

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9VRS4818BKLFT

9VRS4818BKLFT

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