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ADDI7100BCPZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Data Sheet ADDI7100
Rev. D | Page 3 of 20
SPECIFICATIONS
GENERAL SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = DVDD = DRVDD = 3 V, f
SAMP
= 45 MHz, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit
TEMPERATURE RANGE
Operating −25 +85 °C
Storage −65 +150 °C
POWER SUPPLY VOLTAGE
Analog, Digital, Digital Driver 2.7 3.6 V
POWER CONSUMPTION
Normal Operation 125 mW
Full Standby Mode 1 mW
MAXIMUM CLOCK RATE 45 MHz
DIGITAL SPECIFICATIONS
DRVDD = DVDD = 2.7 V, C
L
= 20 pF, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage V
IH
2.1 V
Low Level Input Voltage V
IL
0.6 V
High Level Input Current
IH
10
µA
Low Level Input Current I
IL
10 µA
Input Capacitance C
IN
10 pF
LOGIC OUTPUTS
High Level Output Voltage, I
OH
= 2 mA V
OH
2.2 V
Low Level Output Voltage, I
OL
= 2 mA V
OL
0.5 V
ADDI7100 Data Sheet
Rev. D | Page 4 of 20
SYSTEM SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = DVDD = DRVDD = 3 V, f
SAMP
= 45 MHz, unless otherwise noted.
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
CDS Input characteristics definition
1
Allowable CCD Reset Transient 0.5 1.2 V
CDS Gain Accuracy VGA gain = 6 dB (Code 15, default value)
−3 dB CDS Gain −2.45 −2.95 −3.45 dB
0 dB CDS Gain Default setting 5.40 5.90 6.40 dB
+3 dB CDS Gain 8.65 9.15 9.65 dB
+6 dB CDS Gain 11.10 11.60 12.10 dB
Maximum Input Range Before Saturation
0 dB CDS Gain Default setting 1.0 V p-p
−3 dB CDS Gain 1.4 V p-p
+6 dB CDS Gain 0.5 V p-p
Maximum CCD Black Pixel Amplitude Positive offset definition
1
0 dB CDS Gain Default setting −100 +200 mV
+6 dB CDS Gain −50 +100 mV
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range
Minimum Gain (VGA Code 15) See Figure 13 for VGA curve 6.0 dB
Maximum Gain (VGA Code 1023) See Variable Gain Amplifier (VGA)
section for VGA gain equation
42.0 dB
BLACK LEVEL CLAMP MEASURED AT ADC OUTPUT
Clamp Level Resolution 2048 Steps
Clamp Level Measured at ADC output
Minimum Clamp Level (Code 0) 0 LSB
Maximum Clamp Level (Code 1023) 511 LSB
ADC
Resolution 12 Bits
Differential Nonlinearity (DNL) −1.0 ±0.5 LSB
No Missing Codes Guaranteed
Full-Scale Input Voltage
2.0
V
VOLTAGE REFERENCE
Reference Top Voltage (REFT) 2.0 V
Reference Bottom Voltage (REFB)
1.0
V
SYSTEM PERFORMANCE Specifications include entire signal chain
Gain Accuracy
Low Gain (VGA Code 15) 6 dB total gain (default CDS, VGA) 5.4 5.9 6.4 dB
Maximum Gain (VGA Code 1023) 41.4 41.9 42.4 dB
Peak Nonlinearity, 1 V Input Signal 6 dB total gain (default CDS, VGA) 0.1 %
Total Output Noise AC grounded input, 6 dB total gain 0.8 LSB rms
Power Supply Rejection (PSR) Measured with step change on supply 45 dB
1
Input signal characteristics are defined as shown in Figure 2.
100mV TYP
OPTICAL BLACK PIXEL
500mV TYP
RESET TRANSIENT
1V TYP
INPUT SIGNAL RANGE
07608-002
Figure 2.
Data Sheet ADDI7100
Rev. D | Page 5 of 20
TIMING SPECIFICATIONS
C
L
= 20 pF, f
SAMP
= 45 MHz, unless otherwise noted. See Figure 3, Figure 4, and Figure 16.
Table 4.
Parameter Symbol Min Typ Max Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period t
CONV
22 ns
DATACLK High/Low Pulse Width t
ADC
9 11 ns
SHP Pulse Width t
SHP
5.5 ns
SHD Pulse Width t
SHD
5.5 ns
CLPOB Pulse Width
1
2 20 Pixels
SHP Rising Edge to SHD Falling Edge t
S3
5.5 ns
SHP Rising Edge to SHD Rising Edge t
S1
9 11 t
CONV
− t
S2
ns
SHD Rising Edge to SHP Rising Edge t
S2
9 11 t
CONV
− t
S1
ns
SHD Rising Edge to SHP Falling Edge t
S4
5.5 ns
Internal Clock Delay t
ID
4 ns
DATA OUTPUTS
Output Delay t
OD
15 ns
Pipeline Delay 15 Cycles
SERIAL INTERFACE
Maximum SCK Frequency (Must Not Exceed Pixel Rate) f
SCLK
40 MHz
SL to SCK Setup Time t
LS
10 ns
SCK to SL Hold Time t
LH
10 ns
SDATA Valid to SCK Rising Edge Setup t
DS
10 ns
SCK Rising Edge to SDATA Valid Hold t
DH
10 ns
1
Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Timing Diagrams
PIXE
L N
PIXEL
N + 1
PIXEL
N + 2
PIXE
L
N + 14
PIXEL
N + 15
t
OD
t
S3
t
S4
t
ID
t
ID
N – 15
N – 14 N – 13 N – 1
N
NOTES
1. RECOMMENDED PLACEMENT FOR DATACLK RISING (ACTIVE) EDGE IS NEAR THE SHP OR SHD RISING
(ACTIVE) EDGE. THE BEST LOCATION FOR LOWEST NOISE WILL BE SYSTEM DEPENDENT.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
SH
P
SHD
DAT
ACLK
OUTPUT
DATA
CCD
SIGNAL
(CCDIN)
t
S1
t
CONV
t
S2
07608-012
Figure 3. CCD Sampling Timing (Default Polarity Settings)
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ADDI7100BCPZRL

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Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 12-Bit 45 MHz CCD Signal Processor
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