OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ADDI7100BCPZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
ADDI7100 Data Sheet
Rev. D | Page 6 of 20
07608-013
CCD
SIGNAL
(CCDIN)
EFFECTIVE PIXELS
CLPOB
OPTICAL BLACK PIXELS
HORIZONT
A
L
BLANKING
DUMMY PIXELS EFFECTIVE PIXELS
PBLK
NOTES
1. CLPOB AND PBLK SHOULD BE ALIGNED WITH THE CCD SIGNAL INPUT (CCDIN).
CLPOB WI
L
L OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB.
2
. PBLK SIGN
A
L IS OPTIONAL. KEEP THE PBLK PIN IN THE INACTIVE STATE IF NOT USED.
3
. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS FIFTEEN DATACLK CYCLES.
O
UTPUT
DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA DUMMY BLACK EFFECTIVE DATA
ACTIVE
ACTIVE
Figure 4. Typical Clamp Timing (Default Polarity Settings)
Data Sheet ADDI7100
Rev. D | Page 7 of 20
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
AVDD to AVSS −0.3 V to +3.9 V
DVDD to DVSS
−0.3 V to +3.9 V
DRVDD to DRVSS −0.3 V to +3.9 V
Digital Outputs to DRVSS −0.3 V to DRVDD + 0.3 V
SHP, SHD, DATACLK to DVSS −0.3 V to DVDD + 0.3 V
CLPOB, PBLK to DVSS −0.3 V to DVDD + 0.3 V
SCK, SL, SDATA to DVSS −0.3 V to DVDD + 0.3 V
REFT, REFB, CCDIN to AVSS −0.3 V to AVDD + 0.3 V
Junction Temperature 150°C
Lead Temperature (10 sec) 300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θ
JA
is specified for a device with the exposed bottom pad
soldered to the circuit board ground.
Table 6. Thermal Resistance
Package Type θ
JA
Unit
32-Lead LFCSP 27.7 °C/W
ESD CAUTION
ADDI7100 Data Sheet
Rev. D | Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED
TO THE GROUND PLANE OF THE PCB.
2. NC = NO CONNECT. THIS PIN IS NOT INTERNALLY CONNECTED.
07608-003
24
REFB
23
REFT
22
CCDIN
21
AVSS
20
AVDD
19
SHD
18
SHP
17
CLPOB
1
2
3
4
5
6
7
8
D2
D3
D4
D5
D6
D7
D8
D9
9
10
11
12
13
14
15
16
D10
D11
DRVDD
DRVSS
DVDD
DATACLK
DVSS
PBLK
32
31
30
29
28
27
26
25
D1
D0
NC
NC
VD
SCK
SDATA
SL
ADDI7100
TOP VIEW
(Not to Scale)
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Type
1
Description
1 to 10 D2 to D11 DO Digital Data Outputs.
11 DRVDD P Digital Output Driver Supply.
12 DRVSS P Digital Output Driver Ground.
13 DVDD P Digital Supply.
14 DATACLK DI Digital Data Output Latch Clock.
15 DVSS P Digital Supply Ground.
16 PBLK DI Preblanking Clock Input.
17
CLPOB
DI
Black Level Clamp Clock Input.
18 SHP DI CDS Sampling Clock for CCD Reference Level.
19 SHD DI CDS Sampling Clock for CCD Data Level.
20 AVDD P Analog Supply.
21 AVSS P Analog Ground.
22 CCDIN AI Analog Input for CCD Signal.
23 REFT AO ADC Top Reference Voltage Decoupling.
24 REFB AO ADC Bottom Reference Voltage Decoupling.
25 SL DI Serial Digital Interface Load Pulse.
26 SDATA DI Serial Digital Interface Data Input.
27 SCK DI Serial Digital Interface Clock Input.
28 VD DI Vertical Sync Input. Controls the update time of VD-updated registers. If this pin is not
needed, it should be tied to GND.
29, 30 NC NC No Connect. The pin is not internally connected.
31, 32 D0, D1 DO Digital Data Output.
EPAD Exposed Pad. It is recommended that the exposed pad be soldered to the ground plane
of the printed circuit board (PCB).
1
AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power, and NC = no connect.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

ADDI7100BCPZRL

Mfr. #:
Buy ADDI7100BCPZRL
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 12-Bit 45 MHz CCD Signal Processor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet