Software AN3301
16/35 Doc ID 18161 Rev 1
2.2 Embedded data valid bit
In order to facilitate a more bandwidth efficient for data read, it is possible to program
through Bit[5] of TSC_DET_CFG2 register (0x42) whereby the data valid bit is embedded in
within the first byte of the touch data (FIFO).
Figure 11. TSC data register
In applications whereby no GPIO input/PWM/ADC is used and Pen Down interrupt mode is
selected, it is no longer necessary to read the ISR register. The data valid info can be
obtained through the embedded data valid bit and the touch release info can be obtained
merely by observing the INT pin signal. (ie. INT low: touched; INT high: release).
2.3 Pen down interrupt mode
In Pen down interrupt mode, the INT pin signal is an OR function of the Pen Down and other
enabled GPIO/PWM/ADC interrupts at Port 0 to Port 3.
It is recommended to use Pen Down mode when the GPIO/PWM/ADC functions are not
required or the GPIO/PWM/ADC interrupts are not enabled. In this condition, the INT signal
provides the exclusive indication for touched (INT low) and release (INT high).
AM08680V1
-
[7:0] of Y
[3:0] of X
[11:8] of Y
[11:4] of X
Data valid
status
411
[7:0] of Z[7:0] of Y
[3:0] of X
[11:8] of Y
[11:4] of X
Data valid
status
510
--[7:0] of Y
[3:0] of X
[11:8] of Y
[11:4] of X301
-[7:0] of Z[7:0] of Y
[3:0] of X
[11:8] of Y
[11:4] of X400
Bit[5]
StatusRead
Bit[4]
OpMode
Byte4Byte3Byte2Byte1Byte0
Number of
bytes to
read from
TSC_Data
TSC_DET_CFG2 Register
-
[7:0] of Y
[3:0] of X
[11:8] of Y
[11:4] of X
Data valid
status
411
[7:0] of Z[7:0] of Y
[3:0] of X
[11:8] of Y
[11:4] of X
Data valid
status
510
--[7:0] of Y
[3:0] of X
[11:8] of Y
[11:4] of X301
-[7:0] of Z[7:0] of Y
[3:0] of X
[11:8] of Y
[11:4] of X400
Bit[5]
StatusRead
Bit[4]
OpMode
Byte4Byte3Byte2Byte1Byte0
Number of
bytes to
read from
TSC_Data
TSC_DET_CFG2 Register
RSVDVALIDRSVD
01234567
RSVDVALIDRSVD
01234567
