Software AN3301
24/35 Doc ID 18161 Rev 1
STMPE812A_SetTSCController (STMPE812A_TSC_MAV_20_4, STMPE812A_TSC_NO_PRE,
STMPE812A_TSC_Current20M);
/*Setting the PenStrength [1:0] as ‘Most Sensitive (20K Pull-Up)’, TDetDly [2:0] as
‘40us’ and Settling [2:0] as ‘40us’ in the TSC Detection Configuration 1 Register
(0x41) respectively*/
STMPE812A_ConfigureTSC (STMPE812A_TSC_MOST_SEN, STMPE812A_TSC_TDD40,
STMPE812A_TSC_PDST40);
/*Setting the TSC operating mode OpMode [4] as ’12-bit X, 12-bit Y, 8-bit Z
acquisition’ in the TSC Detection Configuration 2 Register (0x42)*/
STMPE812A_SetTSCOpMode (STMPE812A_DISABLE);
/*Disabling the StatusRead [5] in the TSC Detection Configuration 2 Register (0x42)*/
STMPE812A_SetTSCStatusRead (STMPE812A_DISABLE);
/*Setting the Acq_Mode [7:6] as ‘Data acquisition timed by internal timer’ in the TSC
Detection Configuration 2 Register (0x42)*/
STMPE812A_SetTSCAcquisitionMode (STMPE812A_TSC_INTERNAL_TIMER);
/*Setting the Acq_Mode [7:6] as ‘Data acquisition triggered by a write to “ACQ” bit’
in the TSC Detection Configuration 2 Register (0x42)*/
//STMPE812A_SetTSCAcquisitionMode (STMPE812A_TSC_TRI_ACQ);
/*Setting the Acq_Mode [7:6] as ‘Data acquisition using Host-Controlled Sampling Rate
Control’ in the TSC Detection Configuration 2 Register (0x42)*/
//STMPE812A_SetTSCAcquisitionMode (STMPE812A_TSC_HC_SRC);
/*Setting the TSC sampling rate value of ‘0x0A’ in the TSC Sampling Rate Register
(0x43)*/
STMPE812A_SetTSCSamplingRate (0x0A);
/*Setting the INT_Mode [7] as ‘Normal Interrupt Mode’ in the Interrupt Control
Register (0x08)*/
STMPE812A_SetInterruptMode(STMPE812A_INT_MODE_NORMAL);
/*Setting the INT_Type [1] as ‘Edge Interrupt Type’ in the Interrupt Control Register
(0x08)*/
STMPE812A_SetInterruptType (STMPE812A_INT_TYPE_EDGE);
/*Enabling the Global Interrupt in the Interrupt Control Register (0x08)*/
STMPE812A_EnableGlobalInterrupt (TRUE);
/*Enabling the interrupt from the system related source of TSC_DATA and TSC_RELEASE
to the host in the Interrupt Enable Register (0x09)*/
/*For Acq_Mode [7:6] in the TSC Detection Configuration 2 Register (0x42) is set as
‘Data acquisition timed by internal timer’*/
STMPE812A_EnableInterrupt (STMPE812A_INT_TSC_DATA|STMPE812A_INT_TSC_REL, TRUE);
/*Enabling the interrupt from the system related source of TSC_TOUCH, TSC_DATA and
TSC_RELEASE to the host in the Interrupt Enable Register (0x09)*/
/*For Acq_Mode [7:6] in the TSC Detection Configuration 2 Register (0x42) is set as
either ‘Data acquisition triggered by a write to “ACQ” bit’ (OR) ‘Data acquisition
using Host-Controlled Sampling Rate Control’*/
//STMPE812A_EnableInterrupt
(STMPE812A_INT_TSC_TOUCH|STMPE812A_INT_TSC_DATA|STMPE812A_INT_TSC_REL, TRUE);
/*Enabling the TSC operation in the System Control Register (0x03)*/
STMPE812A_EnableTouchscreen (TRUE);}