843004-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision B January 18, 20162
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Number Name Type Description
1, 2 nQ1, Q1 Output Differential output pair. LVPECL interface levels.
3, 22 V
CCO
Power Output supply pins.
4, 5 Q0, nQ0 Ouput Differential output pair. LVPECL interface levels.
6 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
7 nPLL_SEL Input Pulldown
Selects between the PLL and TEST_CLK as input to the dividers. When LOW,
selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL
Bypass). LVCMOS/LVTTL interface levels.
8 nc Unused No connect.
9V
CCA
Power Analog supply pin.
10, 12
F_SEL0,
F_SEL1
Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
11, 18 V
CC
Power Core supply pin.
13, 14
XTAL_OUT,
XTAL_IN
Input
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
15, 19 V
EE
Power Negative supply pins.
16 TEST_CLK Input Pulldown LVCMOS/LVTTL clock input.
17 nXTAL_SEL Input Pulldown
Selects between crystal or TEST_CLK inputs as the the PLL Reference
source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
20, 21 nQ3, Q3 Output Differential output pair. LVPECL interface levels.
23, 24 Q2, nQ2 Output Differential output pair. LVPECL interface levels.
NOTE:
Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLDOWN
Input Pulldown Resistor 51 kΩ
