843004-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision B January 18, 20168
CRYSTAL INPUT INTERFACE
The 843004-01 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
Figure 2. CRYSTAL INPUt INTERFACE
determined using a 25MHz, 18pF parallel resonant crystal and were
chosen to minimize the ppm error.
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 843004-01 pro-
vides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and
V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each V
CCA
.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
CCA
10μF
.01μF
3.3V
.01μF
V
CC
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left fl oating. Though not
required, but for additional protection, a 1kW resistor can be tied
from XTAL_IN to ground.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can be left
fl oating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the TEST_CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left fl oating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left fl oating or terminated.
