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843004AG-01LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
843004-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision B January 18, 201610
VCC=3.3V
VDD
VCC
Zo = 50 Ohm
+
-
18pF
VCCO
R5
133
RD1
Not Install
To Logic
Input
pins
VCC
Zo = 50 Ohm
RU2
Not Install
3.3V
R9
133
U1
ICS843004-01
1
2
3
4
5
6
7
8
9
10
11
1213
14
15
16
17
18
19
20
21
22
23
24
nQ1
Q1
VCCO
Q0
nQ0
MR
nPLL_SEL
NC
VCCA
F_SEL0
VCC
F_SEL1XTAL_OUT
XTAL_IN
VEE
TEST_CLK
nXTAL_SEL
VCC
VEE
nQ3
Q3
VCCO
Q2
nQ2
VCC
C3
10uF
+
-
R3
133
C7
0.1u
X1
25MHz
Zo = 50 Ohm
R7
133
3.3V
VDD
R6
82.5
VCCA
C4
0.01u
C8
0.1u
V CCO=3.3V
Logic Control Input Examples
C6
0.1u
C2
33pF
C9
0.1u
R2
10
RU1
1K
R4
82.5
Set Logic
Input to
'1'
C1
27pF
To Logic
Input
pins
R10
82.5
Zo = 50 Ohm
R8
82.5
Set Logic
Input to
'0'
VCCO
RD2
1K
LAYOUT GUIDELINE
Figure 5 shows a schematic example of the 843004-01. An example
of LVEPCL termination is shown in this schematic. Additional
LVPECL termination approaches are shown in the LVPECL
Termination Application Note. In this example, an 18pF parallel
FIGURE 5. 843004-01 SCHEMATIC EXAMPLE
resonant 25MHz crystal is used. The C1=27pF and C2=33pF are
recommended for frequency accuracy. For different board layout,
the C1 and C2 may be slightly adjusted for optimizing frequency
accuracy.
843004-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision B January 18, 201611
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 843004-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843004-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 135mA = 467.8mW
• Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power
_MAX
(3.465V, with all outputs switching) = 467.8mW + 120mW = 587.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming a
moderate air fl ow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.588W * 65°C/W = 123.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the
type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ
JA
FOR 24-PIN TSSOP, FORCED CONVECTION
θ
JA
by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W 65°C/W 62°C/W
843004-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision B January 18, 201612
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination
voltage of V
CC
- 2V.
• For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.9V
(V
CCO_MAX
- V
OH_MAX
)
= 0.9V
• For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
– 1.7V
(V
CCO_MAX
- V
OL_MAX
)
= 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC
_MAX
- V
OH_MAX
))
/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC
_MAX
- V
OL_MAX
))
/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

843004AG-01LF

Mfr. #:
Buy 843004AG-01LF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 4 LVPECL OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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