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ADG714BRUZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
–4–
ADG714/ADG715–SPECIFICATIONS
1
DUAL SUPPLY
B Version
–40C
Parameter +25C to +85C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range V
SS
to V
DD
V
On Resistance (R
ON
) 2.5 Ω typ V
S
= V
SS
to V
DD
, I
DS
= 10 mA
4.5 5 Ω max
On Resistance Match Between Channels (ΔR
ON
) 0.4 Ω typ V
S
= V
SS
to V
DD
, I
DS
= 10 mA
0.8 Ω max
On Resistance Flatness (R
FLAT(ON)
) 0.6 Ω typ V
S
= V
SS
to V
DD
, I
DS
= 10 mA
1 Ω max
LEAKAGE CURRENTS V
DD
= +2.75 V, V
SS
= –2.75 V
Source OFF Leakage I
S
(OFF) ± 0.01 nA typ V
S
= +2.25 V/–1.25 V, V
D
= –1.25 V/+2.25 V
± 0.1 ± 0.3 nA max
Drain OFF Leakage I
D
(OFF) ± 0.01 nA typ V
S
= +2.25 V/–1.25 V, V
D
= –1.25 V/+2.25 V
± 0.1 ± 0.3 nA max
Channel ON Leakage I
D
, I
S
(ON) ± 0.01 nA typ V
S
= V
D
= +2.25 V/–1.25 V
± 0.1 ± 0.3 nA max
DIGITAL INPUTS
Input High Voltage, V
INH
1.7 V min
Input Low Voltage, V
INL
0.7 V max
Input Current, I
INL
or I
INH
0.005 μA typ V
IN
= V
INL
or V
INH
± 0.1 μA max
C
IN
, Digital Input Capacitance
2
3 pF typ
DIGITAL OUTPUT ADG714 DOUT
2
Output Low Voltage 0.4 V max
I
SINK
= 6 mA
C
OUT
Digital Output Capacitance 4 pF typ
DIGITAL INPUTS (SCL, SDA)
2
Input High Voltage, V
INH
0.7 V
DD
V min
V
DD
+ 0.3 V max
Input Low Voltage, V
INL
–0.3 V min
0.3 V
DD
V max
I
IN
, Input Leakage Current 0.005 μA typ V
IN
= 0 V to V
DD
± 1 μA max
V
HYST
, Input Hysteresis 0.05 V
DD
V min
C
IN
, Input Capacitance 6 pF typ
LOGIC OUTPUT (SDA)
2
V
OL
, Output Low Voltage 0.4 V max I
SINK
= 3 mA
0.6 V max I
SINK
= 6 mA
DYNAMIC CHARACTERISTICS
2
t
ON
ADG714 20 ns typ V
S
= 1.5 V, R
L
= 300 Ω, C
L
= 35 pF
32 ns max
t
ON
ADG715 133 ns typ V
S
= 1.5 V, R
L
= 300 Ω, C
L
= 35 pF
200 ns max
t
OFF
ADG714 8 ns typ V
S
= 1.5 V, R
L
= 300 Ω, C
L
= 35 pF
18 ns max
t
OFF
ADG715 124 ns typ V
S
= 1.5 V, R
L
= 300 Ω, C
L
= 35 pF
190 ns max
Break-Before-Make Time Delay, t
D
8 ns typ V
S
= 1.5 V, R
L
= 300 Ω, C
L
= 35 pF
1 ns min
Charge Injection ± 3 pC typ V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF
Off Isolation –60 dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 10 MHz
–80 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz
Channel-to-Channel Crosstalk –70 dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 10 MHz
–90 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz
–3 dB Bandwidth 155 MHz typ R
L
= 50 Ω, C
L
= 5 pF
C
S
(OFF) 11 pF typ
C
D
(OFF) 11 pF typ
C
D
, C
S
(ON) 22 pF typ
POWER REQUIREMENTS V
DD
= +2.75 V, V
SS
= –2.75 V
I
DD
15 μA typ Digital Inputs = 0 V or
25 μA max
I
SS
15 μA typ
25 μA max
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
(V
DD
= +2.5 V ± 10%, V
SS
= −2.5 V ± 10%, GND = 0 V unless otherwise noted.)
V
DD
REV.
D
ADG714/ADG715
–5–
ADG714 TIMING CHARACTERISTICS
1, 2
Parameter Limit at T
MIN
, T
MAX
Unit Conditions/Comments
f
SCLK
30 MHz max
t
1
33 ns min
t
2
13 ns min
t
3
13 ns min
t
4
0 ns min
t
5
5 ns min
t
6
4.5 ns min
t
7
0 ns min
t
8
33 ns min
t
9
3
20 ns max
SCLK Cycle Frequency
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Rising Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SCLK Rising Edge to DOUT Valid
NOTES
1
See Figure 1.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
C
L
= 20 pF, R
L
= 1 kΩ.
Figure 1. 3-Wire Serial Interface Timing Diagram
(V
DD
= 2.7 V to 5.5 V. All specifications –40C to +85C unless otherwise noted.)
t
10
t
11
0
6
ns min
ns min
SYNC Rising Edge to SCLK Rising Edge
REV.
D
SCLK Falling Edge to SYNC Falling Edge
SCLK
SYNC
DIN
DOUT
t
1
t
2
t
4
t
6
t
5
t
9
t
8
t
3
t
7
t
11
DB0DB7
DB7* DB6* DB2* DB1* DB0*
t
10
*DATA FROM PREVIOUS WRITE CYCLE
ADG714/ADG715
–6–
REV.
ADG715 TIMING CHARACTERISTICS
1
Parameter Limit at T
MIN
, T
MAX
Unit Conditions/Comments
f
SCL
400 kHz max SCL Clock Frequency
t
1
2.5 μs min SCL Cycle Time
t
2
0.6 μs min t
HIGH
, SCL High Time
t
3
1.3 μs min t
LOW
, SCL Low Time
t
4
0.6 μs min t
HD, STA
, Start/Repeated Start Condition Hold Time
t
5
100 ns min t
SU, DAT
, Data Setup Time
t
6
2
0.9 μs max t
HD, DAT
, Data Hold Time
0 μs min
t
7
0.6 μs min t
SU, STA
, Setup Time for Repeated Start
t
8
0.6 μs min t
SU, STO
, Stop Condition Setup Time
t
9
1.3 μs min t
BUF
, Bus Free Time Between a STOP Condition and
a Start Condition
t
10
300 ns max t
R
, Rise Time of Both SCL and SDA When Receiving
20 + 0.1C
b
3
ns min
t
11
250 ns max t
F
, Fall Time of SDA When Receiving
t
11
300 ns max t
F
, Fall Time of SDA When Transmitting
0.1C
b
3
ns min
C
b
400 pF max Capacitive Load for Each Bus Line
t
SP
4
50 ns max Pulsewidth of Spike Suppressed
NOTES
1
See Figure 2.
2
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
3
C
b
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
4
Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
SDA
SCL
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t
8
t
1
t
7
t
4
t
5
t
11
t
2
t
6
t
10
t
3
t
4
t
9
Figure 2. 2-Wire Serial Interface Timing Diagram
(V
DD
= 2.7 V to 5.5 V. All specifications –40C to +85C unless otherwise noted.)
D
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ADG714BRUZ-REEL7

Mfr. #:
Buy ADG714BRUZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog Switch ICs 2.5 Ohm 2.7V CMOS Octal SPST
Lifecycle:
New from this manufacturer.
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